IP Library Granted Patent US 10,726,936
Granted Patent B2
US 10,726,936 · App. 16/228,387 · Granted Jul 28, 2020

Bad block management for memory sub-systems

Inventor: Roland J. Awusie (Boise, ID)
Assignee: MICRON TECHNOLOGY, INC.
G11C29/44G11C29/38G11C11/5621G11C16/0483
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Quick Facts
Patent No.
US 10,726,936
App. No.
16/228,387
Granted
Jul 28, 2020
Kind
B2
Abstract

A first group of data blocks of a memory sub-system is determined. The first group of data blocks is associated with a failure condition. Also, a second group of data blocks of the memory sub-system is determined. The second group of data blocks is not associated with the failure condition. User data is received and system data of the memory sub-system that is associated with the user data is generated. The system data is stored at the first group of data blocks that is associated with the failure condition by using a first programming operation. The user data is stored at the second group of data blocks that is not associated with the failure condition by using a second programming operation. The second programming operation is different from the first programming operation.

Claims (52)

1. A method comprising:

determining a first plurality of data blocks of a memory sub-system, wherein the first plurality of data blocks is associated with a failure condition;

determining a second plurality of data blocks of the memory sub-system, wherein the second plurality of data blocks is not associated with the failure condition;

receiving user data;

generating system data of the memory sub-system, the system data being associated with the user data;

storing the system data at the first plurality of data blocks that is associated with the failure condition by using a first programming operation; and

storing, by a processing device, the user data at the second plurality of data blocks that is not associated with the failure condition by using a second programming operation that is different than the first programming operation.

2. The method of claim 1 , wherein the first programming operation corresponds to storing a first number of bits per memory cell of the first plurality of data blocks that is to store the system data and the second programming operation corresponds to programming a second number of bits per memory cell of the second plurality of data blocks that is to store the user data, and wherein the second number of bits per memory cell is larger than the first number of bits per memory cell.

3. The method of claim 1 , wherein determining the first plurality of data blocks that is associated with the failure condition comprises:

determining that a read operation on a particular data block that stored particular user data by using the second programming operation has failed to retrieve the stored particular user data; and

determining that the particular data block is associated with the failure condition in response to determining that the read operation has failed.

4. The method of claim 1 , wherein determining the first plurality of data blocks that is associated with the failure condition comprises:

determining that a write operation on a particular data block to store particular user data by using the second programming operation has failed; and

determining that the particular data block is associated with the failure condition in response to determining that the write operation has failed.

5. The method of claim 1 , wherein the first programming operation is a single-level cell (SLC) programming operation and the second programming operation is a programming operation that stores a plurality of bits per each memory cell.

6. The method of claim 1 , wherein the system data corresponds to a characteristic of the memory sub-system at a time when the user data is stored at the memory sub-system.

7. The method of claim 1 , wherein the system data corresponds to metadata for the user data that is received from a host system of the memory sub-system.

8. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

determine a first plurality of data blocks of a memory sub-system, wherein the first plurality of data blocks is associated with a failure condition;

determine a second plurality of data blocks of the memory sub-system, wherein the second plurality of data blocks is not associated with the failure condition;

receive user data;

generate system data of the memory sub-system, the system data being associated with the user data;

store the system data at the first plurality of data blocks that is associated with the failure condition by using a first programming operation; and

store the user data at the second plurality of data blocks that is not associated with the failure condition by using a second programming operation that is different than the first programming operation.

9. The system of claim 8 , wherein the first programming operation corresponds to storing a first number of bits per memory cell of the first plurality of data blocks that is to store the system data and the second programming operation corresponds to programming a second number of bits per memory cell of the second plurality of data blocks that is to store the user data, and wherein the second number of bits per memory cell is larger than the first number of bits per memory cell.

10. The system of claim 8 , wherein to determine the first plurality of data blocks that is associated with the failure condition, the processing device is to:

determine that a read operation on a particular data block that stored particular user data by using the second programming operation has failed to retrieve the stored particular user data; and

determine that the particular data block is associated with the failure condition in response to determining that the read operation has failed.

11. The system of claim 8 , wherein to determine the first plurality of data blocks is associated with the failure condition, the processing device is to:

determine that a write operation on a particular data block to store particular user data by using the second programming operation has failed; and

determine that the particular data block is associated with the failure condition in response to determining that the write operation has failed.

12. The system of claim 8 , wherein the first programming operation is a single-level cell (SLC) programming operation and the second programming operation is a programming operation that stores a plurality of bits per each memory cell.

13. The system of claim 8 , wherein the system data corresponds to a characteristic of the memory sub-system at a time when the user data is stored at the memory sub-system.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

determine a first plurality of data blocks of a memory sub-system, wherein the first plurality of data blocks is associated with a failure condition;

determine a second plurality of data blocks of the memory sub-system, wherein the second plurality of data blocks is not associated with the failure condition;

receive user data;

generate system data of the memory sub-system, the system data being associated with the user data;

store the system data at the first plurality of data blocks that is associated with the failure condition by using a first programming operation; and

store the user data at the second plurality of data blocks that is not associated with the failure condition by using a second programming operation that is different than the first programming operation.

15. The non-transitory computer-readable storage medium of claim 14 , wherein the first programming operation corresponds to storing a first number of bits per memory cell of the first plurality of data blocks that is to store the system data and the second programming operation corresponds to programming a second number of bits per memory cell of the second plurality of data blocks that is to store the user data, and wherein the second number of bits per memory cell is larger than the first number of bits per memory cell.

16. The non-transitory computer-readable storage medium of claim 14 , wherein to determine the first plurality of data blocks that is associated with the failure condition. The processing device is further to:

determine that a read operation on a particular data block that stored particular user data by using the second programming operation has failed to retrieve the stored particular user data; and

determine that the particular data block is associated with the failure condition in response to determining that the read operation has failed.

17. The non-transitory computer-readable storage medium of claim 14 , wherein to determine the first plurality of data blocks that is associated with the failure condition, the processing device is further to:

determine that a write operation on a particular data block to store particular user data by using the second programming operation has failed; and

determine that the particular data block is associated with the failure condition in response to determining that the write operation has failed.

18. The non-transitory computer-readable storage medium of claim 14 , wherein the first programming operation is a single-level cell (SLC) programming operation and the second programming operation is a programming operation that stores a plurality of bits per each memory cell.

19. The non-transitory computer-readable storage medium of claim 14 , wherein the system data corresponds to a characteristic of the memory sub-system at a time when the user data is stored at the memory sub-system.

20. The non-transitory computer-readable storage medium of claim 14 , wherein the system data corresponds to metadata for the user data that is received from a host system of the memory sub-system.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2018
From: AWUSIE, ROLAND J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047836/0413 →