IP Library Granted Patent US 10,411,708
Granted Patent B1
US 10,411,708 · App. 16/228,156 · Granted Sep 10, 2019

Apparatuses and methods including configurable logic circuits and layout thereof

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Quick Facts
Patent No.
US 10,411,708
App. No.
16/228,156
Granted
Sep 10, 2019
Kind
B1
Abstract

Embodiments of the disclosure are drawn to apparatuses and methods for arranging configurable logic circuits such that the configurable logic circuit may be configured to form one or more of several logic circuits by coupling a combination of nodes included in the logic circuit. Configuring the configurable logic circuit may include modification of a single wiring layer.

Claims (33)

1. An apparatus comprising:

a diffusion layer including an N-region and a P-region;

a gate wiring layer disposed adjacent to the diffusion layer, wherein the gate wiring layer includes:

a first section having a T-shape, wherein at least a portion of a stem of the T-shape extends between the N-region and the P-region, at least a first portion of an arm of the T-shape extends over the N-region, and at least a second portion of the arm of the T-shape extends over the P-region;

a second section having a first L-shape, wherein at least a portion of a stem of the first L-shape extends parallel to the stem of the T-shape and at least a portion of an arm of the first L-shape extends over the N-region parallel to the first portion of the arm of the T-shape, wherein the arm of the first L-shape is proximal to the stem of the T-shape; and

a third section having a second L-shape, wherein at least a portion of a stem of the second L-shape extends parallel to the stem of the T-shape and at least a portion of an arm of the second L-shape extends over the P-region parallel to the second portion of the arm of the T-shape, wherein the arm of the second L-shape is distal to the stem of the T-shape; and

a first wiring layer disposed adjacent to the gate wiring layer, wherein the gate wiring layer is disposed between the first wiring layer and the diffusion layer, wherein the first wiring layer includes:

a first plurality of nodes; and

a second plurality of nodes.

2. The apparatus of claim 1 , wherein the first plurality of nodes comprises:

a first node coupled to the stem of the first L-shape and the stem of the second L-shape;

a second node coupled to the N-region between the stem of the first L-shape and the first portion of the arm of the T-shape;

a third node coupled to the P-region adjacent to the second portion of the arm of the T-shape, the third node proximal to the stem of the T-shape; and

a fourth node coupled to the P-region adjacent to the arm of the second L-shape, the fourth node distal to the stem of the T-shape.

3. The apparatus of claim 2 , wherein the first plurality of nodes further comprises a fifth node configured to be coupled to a voltage source.

4. The apparatus of claim 1 , wherein the first plurality of nodes comprises:

a first node coupled to the stem of the first L-shape and the stem of the second L-shape;

a second node coupled to the P-region between the stem of the second L-shape and the second portion of the arm of the T-shape;

a third node coupled to the P-region adjacent to the second portion of the arm of the T-shape, the third node proximal to the stem of the T-shape; and

a fourth node coupled to the P-region adjacent to the arm of the second L-shape, the fourth node distal to the stem of the T-shape.

5. The apparatus of claim 1 , wherein the second plurality of nodes comprises:

a first node coupled to the stem of the T-shape distal to the arm of the T-shape;

a second node coupled to the P-region between the stem of the second L-shape and the second portion of the arm of the T-shape;

a third node coupled to the N-region adjacent to the arm of the first L-shape, the third node proximal to the stem of the T-shape; and

a fourth node coupled to the N-region adjacent to the first portion of the arm of the T-shape, the fourth node distal to the stem of the T-shape.

6. The apparatus of claim 5 , wherein the second plurality of nodes further includes a fifth node configured to be coupled to a ground.

7. The apparatus of claim 1 , wherein the second plurality of nodes comprises:

a first node coupled to the stem of the T-shape distal to the arm of the T-shape;

a second node coupled to the N-region between the stem of the first L-shape and the first portion of the arm of the T-shape;

a third node coupled to the N-region adjacent to the arm of the first L-shape, the third node proximal to the stem of the T-shape; and

a fourth node coupled to the N-region adjacent to the first portion of the arm of the T-shape, the fourth node distal to the stem of the T-shape.

8. The apparatus of claim 1 , further comprising a second wiring layer, wherein the second wiring layer may be coupled to a combination of nodes comprising nodes from the first plurality of nodes and the second plurality of nodes.

9. The apparatus of claim 8 , wherein the combination of nodes coupled by the second wiring layer forms an inverter circuit, a NAND circuit, a NOR circuit, a multiplexer circuit, or a disabled circuit.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2018
From: OTA, KEN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047835/0396 →