Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor
View Patent ↗A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.
1. A tier of memory cells comprising:
a first memory cell and a second memory cell laterally adjacent the first memory cell;
the first memory cell comprising:
a first capacitor and a first vertical transistor;
the first vertical transistor comprising a first pillar comprising a channel and an upper source/drain region above the channel of the first vertical transistor, the channel of the first vertical transistor being above and electrically coupled to a digit line; and
the first capacitor comprising a first bottom electrode directly against a lateral side of the upper source/drain region of the first vertical transistor;
the second memory cell comprising:
a second capacitor and a second vertical transistor;
the second vertical transistor comprising a second pillar comprising a channel and an upper source/drain region above the channel of the second vertical transistor, the channel of the second vertical transistor being above and electrically coupled to the digit line; and
the second capacitor comprising a second bottom electrode directly against a lateral side of the upper source drain region of the second vertical transistor; and
the first capacitor and the second capacitor sharing a common top electrode.
2. The tier of memory cells of claim 1 wherein at least a portion of a gate of the first vertical transistor and at least a portion of a gate of the second vertical transistor are laterally between the channel of the first vertical transistor and the channel of the second vertical transistor, the gate of the first vertical transistor being separated from the gate of the second vertical transistor by an insulative material.
3. The tier of memory cells of claim 1 wherein each of the first bottom electrode and the second bottom electrode is a cylinder.
4. The tier of memory cells of claim 3 wherein each of the cylinders is an upwardly open cylinder.
5. The tier of memory cells of claim 3 wherein each of the cylinders is a downwardly open cylinder.
6. The tier of memory cells of claim 3 wherein each of the cylinders is an upwardly open and downwardly open cylinder.
7. The tier of memory cells of claim 1 wherein,
the channel of the first vertical transistor has a vertical sidewall that is aligned with a vertical sidewall of the upper source/drain region of the first transistor; and
the channel of the second vertical transistor has a vertical sidewall that is aligned with a vertical sidewall of the upper source/drain region of the second transistor.
8. The tier of memory cells of claim 1 wherein,
the channel of the first vertical transistor has a vertical sidewall that is aligned with a vertical sidewall of the first bottom electrode; and
the channel of the second vertical transistor has a vertical sidewall that is aligned with a vertical sidewall of the second bottom electrode.
9. The tier of memory cells of claim 8 wherein,
the vertical sidewall of the channel of the first vertical transistor is aligned with a vertical sidewall of the upper source/drain region of the first transistor; and
the vertical sidewall of the channel of the second vertical transistor is aligned with a vertical sidewall of the upper source/drain region of the second transistor.
10. The tier of memory cells of claim 1 wherein the first and the second bottom electrodes comprise TiN.
11. The tier of memory cells of claim 1 wherein,
each of the channel of the first vertical transistor and the channel of the second vertical transistor has a pair of laterally opposing sides;
each of the first vertical transistor and the second vertical transistor comprises a gate;
the gate of the first vertical transistor being laterally over each of the pair of laterally opposing sides of the channel of the first vertical transistor; and
the gate of the second vertical transistor being laterally over each of the pair of laterally opposing sides of the channel of the second vertical transistor.
12. The tier of memory cells of claim 11 wherein,
the gate of the first vertical transistor does not radially surround the channel of the first vertical transistor; and
the gate of the second vertical transistor does not radially surround the channel of the second vertical transistor.
13. The tier of memory cells of claim 1 wherein each of the first vertical transistor and the second vertical transistor comprises a gate comprising TiN.
14. The tier of memory cells of claim 1 comprising a capacitor insulator between the first bottom electrode and the common top electrode and between the second bottom electrode and the common top electrode, the capacitor insulator being across tops of the first and second pillars, the common top electrode being across the tops of the first and second pillars above the capacitor insulator that is across the tops of the first and second pillars.
15. The tier of memory cells of claim 1 wherein each of the first bottom electrode and the second bottom electrode is a cylinder, and further comprising:
a capacitor insulator between the first bottom electrode and the common top electrode and between the second bottom electrode and the common top electrode; and
the capacitor insulator and the common top electrode being on internal and external sides of the cylinder of each of the first and second bottom electrodes.
16. The tier of memory cells of claim 1 wherein each of the first vertical transistor and the second vertical transistor comprises a gate, the upper source/drain region of each of the first and second vertical transistors having a top that is higher than a top of each of the gates.
17. The tier of memory cells of claim 1 wherein,
the first bottom electrode surrounds and is directly against all uppermost lateral sides of the upper source/drain region of the first vertical transistor; and
the second bottom electrode surrounds and is directly against all uppermost lateral sides of the upper source/drain region of the second vertical transistor.
18. The tier of memory cells of claim 1 wherein each of the upper source/drain region of each of the first and second vertical transistors has a top, the common top electrode comprising at least a portion thereof that is lower than the top of each of the first and second vertical transistors.
19. The tier of memory cells of claim 1 wherein the first and second memory cells each have a total of only one transistor and a total of only one capacitor.
20. The tier of memory cells of claim 1 wherein the first and second memory cells each have a total of only two transistors and a total of only one capacitor.
21. Multiple stacked tiers of memory cells, individual of the tiers of memory cells comprising:
a first memory cell and a second memory cell laterally adjacent the first memory cell;
the first memory cell comprising:
a first capacitor and a first vertical transistor;
the first vertical transistor comprising a first pillar comprising a channel and an upper source/drain region above the channel of the first vertical transistor, the channel of the first vertical transistor being above and electrically coupled to a digit line; and
the first capacitor comprising a first bottom electrode directly against a lateral side of the upper source/drain region of the first vertical transistor;
the second memory cell comprising:
a second capacitor and a second vertical transistor;
the second vertical transistor comprising a second pillar comprising a channel and an upper source/drain region above the channel of the second vertical transistor, the channel of the second vertical transistor being above and electrically coupled to the digit line; and
the second capacitor comprising a second bottom electrode directly against a lateral side of the upper source drain region of the second vertical transistor;
the first capacitor and the second capacitor sharing a common top electrode; and
the first and second memory cells each have a total of only one transistor and a total of only one capacitor.
22. Multiple stacked tiers of memory cells, individual of the tiers of memory cells comprising:
a first memory cell and a second memory cell laterally adjacent the first memory cell;
the first memory cell comprising:
a first capacitor and a first vertical transistor;
the first vertical transistor comprising a first pillar comprising a channel and an upper source/drain region above the channel of the first vertical transistor, the channel of the first vertical transistor being above and electrically coupled to a digit line; and
the first capacitor comprising a first bottom electrode directly against a lateral side of the upper source/drain region of the first vertical transistor;
the second memory cell comprising:
a second capacitor and a second vertical transistor;
the second vertical transistor comprising a second pillar comprising a channel and an upper source/drain region above the channel of the second vertical transistor, the channel of the second vertical transistor being above and electrically coupled to the digit line; and
the second capacitor comprising a second bottom electrode directly against a lateral side of the upper source drain region of the second vertical transistor; and
the first capacitor and the second capacitor sharing a common top electrode.
23. The tier of memory cells of claim 22 wherein the first and second memory cells each have a total of only two transistors and a total of only one capacitor.