Methods and apparatuses for signal translation in a buffered memory

1. A apparatus comprising:

a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol;

a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, the second input/output circuit further comprises a multilevel decoder circuit configured to decode the second signal to provide a plurality of parallel data bits; and

a deserializer circuit configured to convert the plurality of parallel data bits to a plurality of serial data bits, wherein the deserializer circuit comprises:

a first passgate configured to provide a first serial data bit of the plurality of serial data bits at a first time, and

a second passgate configured to provide a second serial data bit of the plurality of serial data bits at a second time.

2. The apparatus of claim 1 , further comprising a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

3. The apparatus of claim 2 , wherein the deserializer circuit is configured to convert the plurality of serial data bits of the first signal to the plurality of parallel data bits.

4. The apparatus of claim 1 , wherein the deserializer circuit comprises:

a first latch configured to latch the first serial data bit of the plurality of serial data bits at the first time; and

a second latch configured to latch the second serial data bit of the plurality of serial data bits at the second time.

5. The apparatus of claim 1 , further comprising a parallel data synchronization circuit configured to synchronize the plurality of parallel data bits.

6. The apparatus of claim 5 , wherein the second input/output circuit comprises a multilevel transmitter circuit configured to encode the synchronized plurality of parallel data bits as a multilevel signal for transmission as the second signal.

7. The apparatus of claim 1 , further comprising a timing circuit configured to provide a first clock signal having a first frequency to the first input/output circuit and a second clock signal having a second frequency to the second input/output circuit, wherein the first signal is received at the first input/output circuit based on the first clock signal and the second signal is received at the second input/output circuit based on the second clock signal.

8. An apparatus comprising:

a first data bus configured to provide a binary signal; and

a data buffer coupled to the first data bus, the data buffer configured to receive the binary signal and to convert the binary signal to a multilevel signal, wherein the data buffer comprises a conversion circuit configured to convert binary signals to multilevel signals and to convert multilevel signals to binary signals, wherein the conversion circuit comprises:

a deserialization circuit comprising a first latch configured to latch a first serial data bit received on the first data bus at a first time and a second latch configured to latch a second serial data bit received on the first data bus at a second time, and

a parallel data synchronization circuit configured to synchronize the first serial data bit and the second data bit to generate first and second parallel data bits, wherein a multilevel transmitter circuit is configured to provide a multilevel signal based on the first and second parallel data bits.

9. The apparatus of claim 8 , further comprising

a second data bus coupled to the data buffer configured to provide the multilevel signal; and

a memory configured to receive the multilevel signal.

10. The apparatus of claim 9 , further comprising

a binary input/output circuit having a binary transmitter circuit and a binary receiver circuit coupled to the first data bus; and

a multilevel input/output circuit having a multilevel transmitter circuit and a multilevel receiver circuit coupled to the second data bus.

11. The apparatus of claim 10 , wherein the data buffer is configured to provide the multilevel signal at a lower frequency than the binary signal.

12. The apparatus of claim 10 , wherein the second data bus is less than 20 mm.

13. The apparatus of claim 8 , wherein the data buffer is further configured to receive a multilevel signal on a second data bus, to convert the multilevel signal to a binary signal, and to provide the binary signal on the first data bus.

14. The apparatus of claim 10 , wherein the conversion circuit is coupled to the binary input/output circuit and the multilevel input/output circuit.

15. The apparatus of claim 10 , wherein the multilevel receiver comprises a multilevel decoder circuit configured to decode multilevel signals and to provide a plurality of parallel data bits.

16. The apparatus of claim 15 , wherein the conversion circuit comprises a serializer circuit configured to serialize the plurality of parallel data bits and to provide a stream of serial data bits to the binary transmitter circuit,

wherein the serializer circuit comprises a first passgate configured to provide a first parallel data bit to the binary transmitter circuit at a first time and to provide a second parallel data bit to the binary transmitter circuit at a second time.

17. A method comprising:

receiving, at a data buffer, a binary data signal comprising a plurality of serial data bits;

converting, by the data buffer, the plurality of serial data bits to a plurality of parallel data bits;

latching, via a first latch, a first serial data bit of the plurality of serial data bits at a first time;

latching, via a second latch, a second serial data bit of the plurality of serial data bits at a second time; and

synchronizing the first serial data bit and the second data bit to generate first and second parallel data bits of the plurality of data bits, wherein a multilevel transmitter circuit is configured to provide a multilevel signal based on the first and second parallel data bits.

18. The method of claim 17 , further comprising:

encoding, by the data buffer, the plurality of parallel data bits in the multilevel signal; and

providing, by the data buffer, the multilevel signal to a memory array.

19. The method of claim 17 , further comprising converting the multilevel signal to the binary data signal, and providing the binary data signal on a first data bus coupled to the data buffer.

20. The method of claim 17 , further comprising providing, via the data buffer, the multilevel signal at a lower frequency than the binary data signal.