IP Library Granted Patent US 10,867,991
Granted Patent B2
US 10,867,991 · App. 16/234,208 · Granted Dec 15, 2020

Semiconductor devices with package-level configurability

Inventors: Kevin G. Duesman (Boise, ID); James E. Davis (Meridian, ID); Warren L. Boyer (Boise, ID); Jeffrey P. Wright (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/0292H01L21/4853H01L23/49838H01L24/16H01L2224/16227H01L2924/1426H01L2924/14511H01L2924/30205
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,867,991
App. No.
16/234,208
Granted
Dec 15, 2020
Kind
B2
Abstract

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first contact pad, and the substrate is electrically isolated from the second contact pad.

Claims (39)

1. A semiconductor device assembly, comprising:

a substrate; and

a die coupled to the substrate, the die including:

a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and

a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements;

wherein the substrate includes a substrate contact electrically coupled to the first contact pad,

wherein the substrate is electrically isolated from the second contact pad, and

wherein the semiconductor device assembly includes no semiconductor dies other than the die.

2. The semiconductor device assembly of claim 1 , wherein the first circuit is a driver circuit.

3. The semiconductor device assembly of claim 1 , wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

4. The semiconductor device assembly of claim 1 , wherein the substrate contact is electrically coupled to the first contact pad by a solder ball.

5. The semiconductor device assembly of claim 1 , wherein the first contact pad is facing the substrate.

6. The semiconductor device assembly of claim 1 , wherein:

the die further includes a third contact pad electrically coupled to a third circuit on the die including only passive circuit elements, and

the substrate contact is electrically coupled to the third contact pad.

7. The semiconductor device assembly of claim 6 , wherein the third circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

8. The semiconductor device assembly of claim 1 , wherein the die is a NAND memory die.

9. A semiconductor device assembly, comprising:

a substrate; and

a die coupled to the substrate, the die including:

a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element,

a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and

a third contact pad electrically coupled to a third circuit on the die including only passive circuit elements;

wherein the substrate includes a substrate contact electrically coupled to the first contact pad by a first solder ball and to the second contact pad by a second solder ball, and

wherein the semiconductor device assembly includes no semiconductor dies other than the die.

10. The semiconductor device assembly of claim 9 , wherein the substrate is electrically isolated from the third contact pad.

11. The semiconductor device assembly of claim 9 , wherein the substrate is electrically coupled to the third contact pad by a third solder ball.

12. The semiconductor device assembly of claim 9 , wherein the first circuit is a driver circuit.

13. The semiconductor device assembly of claim 9 , wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

14. The semiconductor device assembly of claim 9 , wherein the third circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

15. The semiconductor device assembly of claim 9 , wherein the first contact pad is facing the substrate.

16. The semiconductor device assembly of claim 9 , wherein the die is a NAND memory die.

17. A method of making a semiconductor device assembly, comprising:

providing a substrate including a substrate contact;

electrically coupling a first contact pad of a semiconductor die to the substrate contact by a first solder ball, wherein the first contact pad is electrically coupled to a first circuit on the semiconductor die including at least one active circuit element, and

electrically coupling a second contact pad of the semiconductor die to the substrate contact by a second solder ball, wherein the second contact pad is electrically coupled to a second circuit on the semiconductor die including only passive circuit elements,

wherein the semiconductor device assembly includes no semiconductor dies other than the semiconductor die.

18. The method of claim 17 , wherein the first circuit is a driver circuit.

19. The method of claim 17 , wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2018
From: DUESMAN, KEVIN G.; DAVIS, JAMES E.; BOYER, WARREN L.; WRIGHT, JEFFREY P.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047863/0093 →
Continuity (1)
Related Publication 20200212032A1 · Jul 2, 2020