Memory device with a common source select line for two memory portions of a logic sector
A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
1. An apparatus, comprising:
first and second groups of series coupled memory cells included in respective first and second physical memory portions of a first logic sector of a plurality of logic sectors, wherein first source selectors of the first and second groups of series coupled memory cells are coupled to each other to form a common source select line, wherein second drain selectors of the first and second groups of series coupled memory cells are coupled to respective select lines to individually access the first and second groups of series coupled memory cells, respectively, wherein corresponding wordlines of the first and second groups of series coupled memory cells are coupled to one another and coupled together to a respective row driver, and wherein each of the first and second groups of series coupled memory cells is individually addressable based on an activation of the common select line, a corresponding drain selector among the second drain selectors, and a wordline.
2. The apparatus of claim 1 , wherein an access speed of the first logic sector is different from an access speed of a second logic sector of the plurality of logic sectors.
3. The apparatus of claim 1 , further comprising first and second arrays of memory cells,
wherein the first array of memory cells includes the first and second groups of series coupled memory cells included in the first and second physical memory portions of the first logic sector.
4. The apparatus of claim 3 , wherein the second array of memory cells includes third and fourth groups of series coupled memory cells in third and fourth physical memory portions, respectively.
5. The apparatus of claim 4 , wherein the respective row driver is coupled to the first and second arrays of memory cells.
6. The apparatus of claim 5 , further comprising:
third and fourth arrays of memory cells; and
a second row decoder between the third and fourth arrays of memory cells.
7. The apparatus of claim 6 , wherein the first and second arrays have a smaller minimum addressable sector size than the third and fourth arrays.
8. An apparatus, comprising:
first and second groups of series coupled memory cells included in respective first and second physical memory portions of a first logic sector of a plurality of logic sectors, wherein the memory cells of the first and second groups of series coupled memory cells comprise corresponding transistors activated by corresponding wordlines of first and second groups of wordlines, respectively, wherein the corresponding wordlines of the first and second groups of wordlines are coupled to one another;
first and second drain selectors configured to individually select, respectively, the first and second groups of series coupled memory cells included in the first and second respective physical memory portions; and
a common source select line coupled to source selectors in the first and second groups of series coupled memory cells together, wherein each of the first and second group of series coupled memory cells in the first logic sector is individually addressable based on a selection of the common source select line, a corresponding drain selector among the first and second drain selectors, and a wordline.
9. The apparatus of claim 8 , wherein a number of memory cells in the first and second groups of series coupled memory cells in the first logic sector is different from a number of memory cells included in a second logic sector of the plurality of logic sectors.
10. The apparatus of claim 9 , wherein an access speed of the first logic sector is different from an access speed of the second logic sector.
11. An apparatus, comprising:
first and second groups of series coupled memory cells comprising corresponding transistors, wherein the corresponding transistors are activated via corresponding wordlines of first and second groups of wordlines, respectively, wherein the corresponding wordlines of the first and second groups of wordlines are coupled to one another, and wherein the first and second groups of series coupled memory cells are included in a first logic sector of a plurality of logic sectors;
first and second drain lines configured to be individually activated to select, respectively, the first and second groups of series coupled memory cells; and
a common source select line coupled to source selectors in the first and second groups of series coupled memory cells together, wherein each of the first and second group of series coupled memory cells in the first logic sector is individually addressable based on a selection of the common source select line, a corresponding drain line among the first and second drain lines, and a wordline.
12. The apparatus of claim 11 , wherein an access speed of the first logic sector is different from an access speed of a second logic sector of the plurality of logic sectors.
13. The apparatus of claim 11 , wherein the first and second groups of series coupled memory cells are included in first and second respective physical memory portions of the first logic sector, and
wherein a number of memory cells in the first and second groups of series coupled memory cells in the first logic sector is different from a number of memory cells included in a second logic sector of the plurality of logic sectors.