Refresh in non-volatile memory
View Patent ↗The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh a memory cell of an array of memory cells in response to the array of memory cells being accessed a threshold number of accesses.
1. An apparatus, comprising:
an array of memory cells; and
a processor configured to:
determine a refresh rate of the array of memory cells based on a threshold miss rate; and
refresh a memory cell of the array of memory cells based on the refresh rate.
2. The apparatus of claim 1 , wherein the threshold miss rate is based on a number of memory cells that fail to refresh.
3. The apparatus of claim 2 , wherein the number of memory cells fail to refresh within a threshold number of accesses for the memory cell.
4. The apparatus of claim 1 , wherein the memory cell fails in response to being accessed a threshold number of times without being refreshed.
5. The apparatus of claim 2 , wherein the processor is configured to reduce a miss rate by increasing the refresh rate.
6. The apparatus of claim 2 , wherein the refresh rate is at most 1/T, where T is a number of times the memory cell can be accessed before it will fail if not refreshed.
7. The apparatus of claim 2 , wherein the processor is configured to determine the refresh rate periodically based on dynamic data.
8. The apparatus of claim 2 , wherein the processor is configured to determine the refresh rate periodically based on a type of workload.
9. An apparatus, comprising:
an array of memory cells; and
a processor configured to:
determine a threshold miss rate based on a number of memory cells that fail to refresh;
determine a refresh rate of the array of memory cells based on the threshold miss rate; and
refresh a memory cell of the array of memory cells in response to the array of memory cells being accessed a threshold number of accesses, wherein the threshold is based on the refresh rate.
10. The apparatus of claim 9 , wherein the processor is configured to refresh the memory cell of the array of memory cells that was last accessed.
11. The apparatus of claim 9 , wherein the processor is configured to refresh a randomly selected memory cell of the array of memory cells.
12. The apparatus of claim 9 , wherein the processor is configured to refresh a memory cell with an access count that is above a threshold of the array of memory cells.
13. The apparatus of claim 9 , wherein the apparatus includes a counter.
14. A non-transitory computer-readable storage medium containing instructions that when executed cause a processor to:
determine a refresh rate of an array of memory cells based on a threshold miss rate; and
refresh a memory cell of the array of memory cells based on the refresh rate.
15. The non-transitory computer-readable storage medium of claim 14 , further comprising instructions to refresh the memory cell of the array of memory cells in response to the array of memory cells being accessed a threshold number of accesses.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the threshold number of accesses is based on the refresh rate.
17. The non-transitory computer-readable storage medium of claim 14 , further comprising instructions to reduce a miss rate by increasing the refresh rate.
18. The non-transitory computer-readable storage medium of claim 14 , further comprising instructions to determine the refresh rate to reduce write amplification.
19. The non-transitory computer-readable storage medium of claim 14 , further comprising instructions to determine the refresh rate that increases a threshold number of accesses based on the threshold miss rate.
20. The non-transitory computer-readable storage medium of claim 14 , further comprising instructions to determine the refresh rate that makes a threshold 500 accesses or more based on the threshold miss rate.