Sequential data optimized sub-regions in storage devices
View Patent ↗Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
1. A storage system comprising:
a memory array;
a random access memory configured to store at least a portion of one or more logical-to-physical (L2P) mapping tables; and
a memory controller, wherein the memory controller is programmed to perform operations including:
partitioning the memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges;
assigning a first granularity of a first L2P mapping table entry for the first portion of the memory array designated for a first usage;
assigning a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity;
storing data indicative of size of the first granularity and the second granularity in the memory array; and
storing at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in the random access memory.
2. The system of claim 1 , wherein data indicative of size of the first and second granularity are also stored in a region table in the controller.
3. The system of claim 1 , wherein the first granularity is larger than the second granularity.
4. The system of claim 1 , wherein the second granularity is larger than the first granularity.
5. The system of claim 1 , wherein the first portion and the second portion are different memory types.
6. The system of claim 1 , wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup.
7. The system of claim 1 , wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array during runtime.
8. The system of claim 1 , wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup and re-partitioning the memory array during runtime.
9. A method comprising:
partitioning, by a memory controller, a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges;
assigning, by the memory controller, a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage;
assigning, by the memory controller, a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity;
storing, by the memory controller, data indicative of size of the first granularity and the second granularity in the memory array; and
storing, by the memory controller, at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
10. The method of claim 9 , further comprising:
partitioning, by the memory controller, the memory array to include a third portion, the first portion, second portion and third portion having non-overlapping logical block addressing (LBA) ranges; and
assigning, by the memory controller, a third granularity of a third L2P mapping table entry for the third portion of the memory array designated for a third usage.
11. The method of claim 10 , wherein the third granularity is not equal to the first granularity and the second granularity.
12. The method of claim 10 , further comprising:
storing, by the memory controller, the third granularity in the memory array; and
storing, by the memory controller, at least a portion of the third L2P mapping table entry in the L2P cache of the memory controller.
13. The method of claim 10 , further comprising:
partitioning, by the memory controller, the memory array to include a fourth portion, the first portion, second portion, third portion and fourth portion having non-overlapping logical block addressing (LBA) ranges; and
assigning, by the memory controller, a fourth granularity of a fourth L2P mapping table entry for the fourth portion of the memory array designated for a fourth usage.
14. The method of claim 13 , wherein the fourth granularity is not equal to the first granularity, the second granularity and the third granularity.
15. The method of claim 13 , further comprising:
storing, by the memory controller, the fourth granularity in the memory array; and
storing, by the memory controller, at least a portion of the fourth L2P mapping table entry in the L2P cache of the memory controller.
16. A non-transitory computer readable medium comprising instructions thereon that, when executed by a processor, cause the processor to perform operations comprising:
partitioning a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges;
assigning a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage;
assigning a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity;
storing data indicative of size of the first granularity and the second granularity in the memory array; and
storing at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache.
17. The computer readable medium of claim 16 , wherein the first portion and the second portion are different memory types.
18. The computer readable medium of claim 16 , wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup.
19. The computer readable medium of claim 16 , wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array during runtime.
20. The computer readable medium of claim 16 , wherein partitioning the memory array into a first portion and a second portion includes partitioning the memory array at startup and re-partitioning the memory array during runtime.