IP Library Granted Patent US 10,896,042
Granted Patent B2
US 10,896,042 · App. 16/207,786 · Granted Jan 19, 2021

Vector population count determination via comparison iterations in memory

Inventor: Sanjay Tiwari (Meridian, ID)
Assignee: Micron Technology, Inc.
G06F9/3004G06F7/607G06F9/30021G06F9/30036G06F15/7821G06F15/7839
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Quick Facts
Patent No.
US 10,896,042
App. No.
16/207,786
Granted
Jan 19, 2021
Kind
B2
Abstract

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

Claims (32)

1. A method, comprising:

determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array by:

creating an elemental mask that indicates a most significant bit of each of the number of fixed length elements;

determining a number of comparison iterations to perform for determining the vector population count based on a log 2 of a number of bits in the number of fixed length elements and

performing the determined number of comparison iterations, wherein the number of comparison iterations include determining a reduction vector for each of the number of comparison iterations, determining a first portion of a pattern mask based on shifting a result of an AND operation and a second portion of the pattern mask based on an inverse of the reduction vector for each of the number of comparison iterations, and performing a half add operation on the first portion of the pattern mask and the second portion of the pattern mask.

2. The method of claim 1 , wherein performing the number of comparison iterations comprises determining the reduction vector for each of the number of comparison iterations.

3. The method of claim 1 , wherein performing the number of comparison iterations comprises determining the pattern mask for each of the number of comparison iterations.

4. The method of claim 1 , wherein the determining of the vector population count is performed in the memory array.

5. The method of claim 1 , wherein determining the vector population count includes performing a number of AND, OR, and shift operations, wherein the number of AND and shift operations are based on a length of the number of fixed length elements.

6. The method of claim 5 , wherein the number of AND, OR, and shift operations are performed using sensing circuitry coupled to each of a number of columns of complementary sense lines.

7. The method of claim 1 , wherein the determining of the vector population count includes determining how many bits of each of the number of fixed length elements have a particular value.

8. The method of claim 7 , wherein the particular value includes a bit value of 1.

9. The method of claim 7 , wherein the particular value includes a bit value of 0.

10. The method of claim 1 , wherein the vector is stored in a group of memory cells coupled to a common access line.

11. The method of claim 10 , including determining the vector population count and storing a result of the determination of the vector population count in a different group of memory cells coupled to a different access line than the common access line of the memory array without performing a sense line address access.

12. An apparatus, comprising:

a group of memory cells coupled to a first access line of a memory array and configured to store a vector comprising a number of elements; and

a controller configured to:

perform a number of comparison iterations using sensing circuitry to determine a vector population count of the number of elements, wherein the number of comparison iterations include determining a reduction vector for each of the number of comparison iterations, determining a first portion of a pattern mask based on shifting a result of an AND operation and a second portion of the pattern mask based on an inverse of the reduction vector for each of the number of comparison iterations, and performing a half add operation on the first portion of the pattern mask and the second portion of the pattern mask.

13. The apparatus of claim 12 , wherein the sensing circuitry comprises a number of sense amplifiers and a number of compute components.

14. The apparatus of claim 13 , wherein each of the number of sense amplifiers comprise a primary latch and each of the number of compute components comprise a secondary latch.

15. The apparatus of claim 12 , wherein the sensing circuitry is configured to determine a most significant bit of each of the number of elements.

16. The apparatus of claim 15 , wherein the sensing circuitry is configured to store elements representing the most significant bit of each of the number of elements as an elemental mask.

17. The apparatus of claim 12 , wherein the sensing circuitry is configured to determine a number of comparison iterations to perform by calculating log 2 of a number of bits in the number of elements.

18. An apparatus comprising:

a group of memory cells coupled to a first access line of a memory array and configured to store a number of elements; and

a controller configured to:

determine an elemental mask;

perform a number of comparison iterations, wherein each of the number of comparison iterations include determining a reduction vector for each of the number of comparison iterations, wherein determining the reduction vector includes a first loop that determines a shifted elemental mask by shifting bits of the elemental mask to the right by one bit and an OR operation is performed with the shifted elemental mask and the elemental mask and determining a pattern mask for each of the number of comparison iterations; and

output a vector population count that indicates how many bits of each of the number of elements have a particular data value.

19. The apparatus of claim 18 , wherein the sensing circuitry is configured to determine the number of comparison iterations to perform by calculating log 2 of a number of bits in the number of elements.

20. The apparatus of claim 18 , wherein the sensing circuitry is configured to calculate an output for each of the number of comparison iterations that is used by a subsequent comparison iteration to determine the vector population count.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 068806/0637 →
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2018
From: TIWARI, SANJAY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047659/0982 →
Continuity (3)
Continuation 15065483 · Mar 9, 2016
Provisional Application 62132891 · Mar 13, 2015
Related Publication 20190102172A1 · Apr 4, 2019