Apparatuses including memory cells with gaps comprising low dielectric constant materials
Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.
1. An electronic device, comprising:
a pair of dielectric materials located substantially parallel to one another; and
a charge storage material disposed substantially between the pair of dielectric materials and having a first surface and an opposing second surface, the first surface and the second surface being substantially parallel to each of the pair of dielectric materials, respectively, at least the first surface being separated from a closest one of the pair of dielectric materials by a gap, the gap being filled with a low-dielectric-constant material.
2. The electronic device of claim 1 , wherein the low-dielectric-constant material comprises air.
3. The electronic device of claim 1 , wherein low-dielectric-constant material is formed substantially without carbon.
4. The electronic device of claim 1 , wherein low-dielectric-constant material comprises at least one material selected from materials including carbon-doped silicon dioxide, fluorine-doped silicon dioxide, and porous silicon dioxide.
5. The electronic device of claim 4 , further comprising a conductive material disposed between the pair of dielectric materials, wherein the conductive material substantially surrounds an outer periphery of the charge storage material.
6. The electronic device of claim 1 , wherein the charge storage element comprises a substantially toroidal-shaped floating gate.
7. The electronic device of claim 6 , wherein a cross-section of the toroidal-shaped floating gate is substantially rectangular.
8. The electronic device of claim 6 , wherein a cross-section of the toroidal-shaped floating gate is substantially square.
9. The electronic device of claim 6 , wherein the gap is configured to reduce a parasitic capacitance between the toroidal-shaped floating gate and a control gate to a level lower than a parasitic capacitance of a gap formed from a high-k dielectric-constant material.
10. The electronic device of claim 9 , wherein the control gate substantially surrounds an outer periphery of the toroidal floating gate.
11. The electronic device of claim 9 , further comprising a dielectric material arranged between an outer periphery of the toroidal floating gate and an inner periphery of the control gate.
12. An apparatus comprising:
a pair of dielectric materials substantially parallel to one another and to a surface of a substrate;
a conductive material disposed between the pair of dielectric materials; and
a floating gate disposed between the pair of dielectric materials, the floating gate having a first surface and an opposing second surface, at least one of the first surface and the second surface being substantially parallel to and separated from a proximal one of the pair of dielectric materials by an air gap.
13. The apparatus of claim 12 , wherein the gap is configured to reduce a parasitic capacitance between the floating gate and a control gate to a level lower than the parasitic capacitance of a gap formed from a high-k-dielectric material.
14. The apparatus of claim 12 , wherein the apparatus includes a memory device comprising the pair of dielectric materials, the conductive material, and the floating gate.
15. The apparatus of claim 12 , wherein the conductive material substantially surrounds an outer periphery of the floating gate and forms a control gate.
16. The apparatus of claim 12 , wherein the apparatus further comprises a controller coupled to the memory device.