IP Library Granted Patent US 10,839,881
Granted Patent B2
US 10,839,881 · App. 16/184,276 · Granted Nov 17, 2020

Dual mode ferroelectric memory cell operation

Inventor: Daniele Vimercati (El Dorado Hills, CA)
Assignee: Micron Technology, Inc.
G11C11/2273G11C11/005G11C11/221G11C11/2275G11C11/2293G11C14/0027
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Quick Facts
Patent No.
US 10,839,881
App. No.
16/184,276
Granted
Nov 17, 2020
Kind
B2
Abstract

Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

Claims (56)

1. A method, comprising:

operating a ferroelectric memory cell of a memory array in a non-volatile mode;

initiating a first command to switch the ferroelectric memory cell from the non-volatile mode to a volatile mode;

sensing, based at least in part on the first command, a first logic state of the ferroelectric memory cell based at least in part on a signal from a ferroelectric capacitor of the ferroelectric memory cell;

switching the ferroelectric memory cell from the non-volatile mode to the volatile mode based at least in part on sensing the first logic state;

storing the first logic state in the ferroelectric capacitor of the ferroelectric memory cell after switching the ferroelectric memory cell from the non-volatile mode to the volatile mode; and

operating the ferroelectric memory cell in the volatile mode based at least in part on the first command.

2. The method of claim 1 , wherein initiating the first command comprises:

selecting a first portion of the memory array.

3. The method of claim 1 , further comprising:

initiating a second command while operating the ferroelectric memory cell in the volatile mode; and

operating the ferroelectric memory cell in the non-volatile mode based at least in part on the second command.

4. The method of claim 3 , wherein initiating the second command comprises:

deselecting a first portion of the memory array.

5. The method of claim 1 , further comprising:

operating a second ferroelectric memory cell of the memory array in the non-volatile mode while operating the ferroelectric memory cell in the volatile mode.

6. The method of claim 1 , further comprising:

operating a second ferroelectric memory cell of the memory array in the volatile mode while operating the ferroelectric memory cell in the volatile mode.

7. The method of claim 1 , further comprising:

determining whether the ferroelectric memory cell is in the non-volatile mode or the volatile mode at a first time; and

determining whether a second ferroelectric memory cell of the memory array is in the non-volatile mode or the volatile mode at the first time.

8. The method of claim 7 , further comprising:

adjusting an operation mode of the second ferroelectric memory cell based at least in part on determining whether the second ferroelectric memory cell is in the non-volatile mode or the volatile mode.

9. An apparatus comprising:

a ferroelectric memory cell of a memory array;

a transistor coupled to the ferroelectric memory cell;

a controller in electronic communication with the transistor and a sensing component, wherein the controller is configured to cause the apparatus to:

operate the ferroelectric memory cell in a non-volatile mode;

initiate a first command to switch the ferroelectric memory cell from the non-volatile mode to a volatile mode;

sense, using the sensing component and based at least in part on the first command, a first logic state of the ferroelectric memory cell based at least in part on a signal from a ferroelectric capacitor of the ferroelectric memory cell;

switch the ferroelectric memory cell from the non-volatile mode to the volatile mode based at least in part on sensing the first logic state;

store the first logic state in the ferroelectric capacitor of the ferroelectric memory cell after switching the ferroelectric memory cell from the non-volatile mode to the volatile mode; and

operate the ferroelectric memory cell in the volatile mode based at least in part on the first command.

10. The apparatus claim 9 , wherein the controller is configured to cause the apparatus to:

select a first portion of the memory array, wherein initiating the first command comprises selecting the first portion of the memory array.

11. The apparatus of claim 9 , wherein the controller is configured to cause the apparatus to:

initiate a second command while operating the ferroelectric memory cell in the volatile mode; and

operate the ferroelectric memory cell in the non-volatile mode based at least in part on the second command.

12. The apparatus of claim 11 , wherein the controller is configured to cause the apparatus to:

deselect a first portion of the memory array, wherein initiating the second command comprises deselecting the first portion of the memory array.

13. The apparatus of claim 9 , wherein the controller is configured to cause the apparatus to:

operate a second ferroelectric memory cell of the memory array in the non-volatile mode while operating the ferroelectric memory cell in the volatile mode.

14. The apparatus of claim 9 , wherein the controller is configured to cause the apparatus to:

operate a second ferroelectric memory cell of the memory array in the volatile mode while operating the ferroelectric memory cell in the volatile mode.

15. The apparatus of claim 9 , wherein the controller is configured to cause the apparatus to:

determine whether the ferroelectric memory cell is in the non-volatile mode or the volatile mode at a first time; and

determine whether a second ferroelectric memory cell of the memory array is in the non-volatile mode or the volatile mode at the first time.

16. A method, comprising:

operating a ferroelectric memory cell of a memory array in a volatile mode;

initiating a first command to switch the ferroelectric memory cell from the volatile mode to a non-volatile mode;

sensing, based at least in part on the first command, a first logic state of the ferroelectric memory cell based at least in part on a signal from a ferroelectric capacitor of the ferroelectric memory cell;

switching the ferroelectric memory cell from the volatile mode to the non-volatile mode based at least in part on sensing the first logic state;

storing the first logic state in the ferroelectric capacitor of the ferroelectric memory cell after switching the ferroelectric memory cell from the volatile mode to the non-volatile mode; and

operating the ferroelectric memory cell in the non-volatile mode based at least in part on the first command.

17. The method of claim 1 , further comprising:

connecting the ferroelectric memory cell with a first switch based at least in part on the first command, wherein operating the ferroelectric memory cell in the non-volatile mode is based at least in part on connecting the ferroelectric memory cell with the first switch.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →