Writing to cross-point non-volatile memory
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may have a polarity opposite to the access voltage. A delay may be instituted between access attempts in order to discharge the untargeted memory cells.
1. A method, comprising:
applying a first voltage across a memory cell during an access operation; and
applying, based at least in part on applying the first voltage, a second voltage across the memory cell during a discharge operation.
2. The method of claim 1 , wherein applying the first voltage across the memory cell comprises:
applying a third voltage to a first conductive line coupled with the memory cell; and
applying a fourth voltage to a second conductive line coupled with the memory cell.
3. The method of claim 2 , wherein applying the second voltage across the memory cell comprises:
applying a fifth voltage to the first conductive line; or
applying a sixth voltage to the second conductive line;
or both.
4. The method of claim 3 , wherein the fifth voltage is applied before the sixth voltage is applied, and wherein a magnitude of the fifth voltage and a magnitude the sixth voltage is below a threshold voltage of a selection component coupled with the memory cell.
5. The method of claim 3 , wherein the fifth voltage is applied concurrently with the sixth voltage, and wherein a combined magnitude of the fifth voltage and the sixth voltage is below a threshold voltage of a selection component coupled with the memory cell.
6. The method of claim 1 , further comprising:
applying a third voltage across the memory cell during the access operation and before applying the second voltage across the memory cell, wherein applying the third voltage across the memory cell comprises:
applying a fourth voltage to a first conductive line coupled with the memory cell; and
applying a fifth voltage to a second conductive line coupled with the memory cell.
7. The method of claim 6 , wherein the third voltage has an opposite polarity as the first voltage, and wherein a magnitude of the third voltage is equivalent to a magnitude of the first voltage, the method further comprising:
applying a sixth voltage across the memory cell after applying the second voltage and during the discharge operation.
8. The method of claim 1 , wherein the second voltage has an opposite polarity than the first voltage, and wherein a magnitude of the second voltage is less than a threshold voltage of a selection component coupled with the memory cell.
9. The method of claim 1 , wherein a voltage across a second memory cell that is coupled with the memory cell increases based at least in part on applying the first voltage, and wherein the voltage across the second memory cell decreases based at least in part on applying the second voltage.
10. The method of claim 1 , further comprising:
updating a value of a counter based at least in part on the first voltage being applied across the memory cell, wherein the second voltage is applied based at least in part on the value of the counter.
11. The method of claim 1 , further comprising:
performing a sensing operation of the memory cell during the access operation, wherein the second voltage is applied after the access operation is completed.
12. An apparatus, comprising:
a memory cell;
a biasing component coupled with the memory cell and configured to apply a voltage across the memory cell; and
a monitoring component coupled with the biasing component and configured to detect an application of the voltage across the memory cell by the biasing component.
13. The apparatus of claim 12 , wherein the monitoring component comprises a counter, and wherein the monitoring component is configured to increment a value of the counter based at least in part on detecting the application of the voltage across the memory cell.
14. The apparatus of claim 12 , wherein the monitoring component comprises a timer, wherein the monitoring component is configured to activate the timer based at least in part on detecting the application of the voltage across the memory cell.
15. The apparatus of claim 14 , wherein the biasing component is configured to apply another voltage across the memory cell based at least in part on a state of the timer.
16. The apparatus of claim 12 , further comprising:
a first conductive line coupled with the memory cell, wherein the biasing component is configured to apply the voltage across the memory cell using the first conductive line.
17. The apparatus of claim 16 , further comprising:
a second conductive line;
a selection component coupled with the memory cell and the second conductive line, the selection component configured to electronically isolate the memory cell from the second conductive line.
18. An apparatus, comprising:
a memory cell;
a controller coupled with the memory cell and operable to cause the apparatus to:
apply a first voltage across the memory cell during an access operation; and
apply a second voltage across the memory cell during a discharge operation and after the access operation is completed.
19. The apparatus of claim 18 , further comprising:
a first conductive line coupled with the memory cell; and
a second conductive line coupled with the memory cell, wherein the controller is operable to cause the apparatus to:
apply a third voltage to the first conductive line and a fourth voltage to the second conductive line, wherein applying the first voltage across the memory cell comprises applying the third voltage to the first conductive line and the fourth voltage to the second conductive line.
20. The apparatus of claim 18 , further comprising:
a biasing component coupled with the memory cell; and
a counter coupled with the biasing component, wherein the controller is operable to cause the apparatus to:
update a value of the counter based at least in part on the first voltage being applied across the memory cell.