Ferroelectric memory cell recovery
View Patent ↗Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.
1. A method, comprising:
applying a test voltage to a ferroelectric memory cell of a memory array during an access operation;
determining that the ferroelectric memory cell of the memory array satisfies a threshold based at least in part on applying the test voltage;
applying a recovery voltage to the ferroelectric memory cell as part of a recovery operation on the ferroelectric memory cell based at least in part on determining that the ferroelectric memory cell satisfies the threshold; and
accessing the ferroelectric memory cell during the access operation based at least in part on applying the recovery voltage.
2. The method of claim 1 , wherein the ferroelectric memory cell of the memory array satisfies the threshold comprises:
failing to read a stored logic state on the ferroelectric memory cell based at least in part on applying the test voltage having an amplitude less than an amplitude of an access voltage; or
failing to read the stored logic state on the ferroelectric memory cell based at least in part on a test sense window that is less than a sense window used for a cycle of the ferroelectric memory cell.
3. The method of claim 1 , further comprising:
determining a logic state stored on the ferroelectric memory cell based at least in part on accessing the ferroelectric memory cell; and
storing the logic state of the ferroelectric memory cell, wherein the recovery voltage is applied to the ferroelectric memory cell after storing the logic state of the ferroelectric memory cell and before performing the recovery operation.
4. The method of claim 1 , further comprising:
storing a logic state on the ferroelectric memory cell after applying the recovery voltage during a read operation.
5. The method of claim 1 , wherein a time period when the recovery voltage is applied is based at least in part on an amplitude of the recovery voltage during a read operation.
6. The method of claim 1 , wherein the recovery voltage comprises at least one of:
a plurality of bipolar voltage pulses;
a plurality of unipolar voltage pulses; or
a voltage with a constant amplitude.
7. A method, comprising:
monitoring a timing parameter associated with operation of a ferroelectric memory cell of a memory array;
determining that the ferroelectric memory cell of the memory array satisfies a threshold based at least in part on monitoring the timing parameter; and
performing a recovery operation on the ferroelectric memory cell based at least in part on determining that the ferroelectric memory cell satisfies the threshold.
8. The method of claim 7 , wherein the timing parameter indicates a duration of time since initiating the recovery operation.
9. The method of claim 7 , wherein the timing parameter indicates a count of access operations performed on the ferroelectric memory cell since initiating the recovery operation.
10. The method of claim 7 , further comprising:
determining that the timing parameter exceeds a threshold time period that is based at least in part on the timing parameter to satisfy the threshold.
11. The method of claim 10 , further comprising:
determining that the timing parameter exceeds a threshold number of operations.
12. The method of claim 11 , wherein the timing parameter and the threshold of the ferroelectric memory cell are associated with a number of access operations in which the ferroelectric memory cell has reached a remnant polarization threshold.
13. The method of claim 7 , wherein the timing parameter is monitored by a timer.
14. The method of claim 7 , wherein the timing parameter comprises a number of operations performed on the ferroelectric memory cell since initiating the recovery operation.
15. The method of claim 7 , wherein the timing parameter is monitored by a counter that is incremented after an operation is performed on the ferroelectric memory cell.
16. A method, comprising:
detecting that a logic value of a ferroelectric memory cell of a memory array is corrupted;
determining that the ferroelectric memory cell satisfies a threshold based at least in part on detecting the corrupted logic value; and
performing a recovery operation on the ferroelectric memory cell based at least in part on a determining that the ferroelectric memory cell satisfies the threshold.
17. The method of claim 16 , wherein performing the recovery operation comprises:
applying a recovery voltage to the ferroelectric memory cell based at least in part on determining that the ferroelectric memory cell satisfies the threshold.
18. The method of claim 16 , wherein detecting that the logic value is corrupted comprises:
determining whether the logic value stored in the ferroelectric memory cell is an intended logic value, wherein detecting that the logic value is corrupted is based at least in part on determining whether the logic value is the intended logic value.
19. The method of claim 16 , further comprising:
applying an error correction code to an unknown logic value, wherein detecting that the logic value is corrupted is based at least in part on applying the error correction code.
20. The method of claim 19 , wherein the unknown logic value is corrected by the error correction code.