Vertical two-transistor single capacitor memory cells and memory arrays

1. An integrated assembly, comprising:

a first transistor having a first channel region within a first vertically extending semiconductor pillar and comprising gate material extending vertically along the second channel region on at least two opposing sides of the first vertically extending semiconductor pillar;

a second transistor having a second channel region within a second vertically extending semiconductor pillar and comprising gate material extending vertically along the second channel region on at least two opposing sides of the second vertically extending semiconductor pillar, the first and second transistors being supported by a semiconductor substrate;

a capacitor having a first node electrically coupled with a source/drain region of the first transistor, the first node having vertical sidewall surfaces, having a second node electrically coupled with a source/drain region of the second transistor, the second node extending along a portion of the vertical sidewall surfaces of the first node where the first portion is less than an entirety, and having capacitor dielectric material between the first and second nodes;

wherein the first and second transistors are not in a common horizontal plane as one another; and

wherein the capacitor is vertically between the first and second transistors, the first vertically extending semiconductor pillar being in direct physical contact with a first comparative bitline and extending from the first comparative bitline to the first node and the second vertically extending semiconductor pillar being in direct physical contact with a second comparative bitline and extending from the second comparative bitline to the second node.

2. A memory cell comprising:

first and second transistors vertically displaced relative to one another, each of the first and second transistors comprising a vertically extending channel region within a semiconductor pillar and having gate material extending vertically along the channel region on at least two opposing sides of the semiconductor pillar, the semiconductor pillar extending vertically above and vertically below the gate material; and

a capacitor disposed to be vertically between the first and second transistors, the capacitor having an inner node electrically coupled and in direct physical contact with a source/drain region of the first transistor, the inner node having vertical sidewall surfaces, the capacitor having an outer node electrically coupled and in direct physical contact with a source/drain region of the second transistor, the outer node surrounding the vertical sidewalls and covering less than an entirety of a vertical height of the vertical sidewalls, the capacitor further comprising capacitor dielectric material between the inner and outer nodes, the semiconductor pillar of the first transistor being in direct physical contact with and extending from a first comparative bitline to the first node and the semiconductor pillar of the second transistor extending from the second node to and in direct physical contact with a second comparative bitline.

3. The memory cell of claim 2 wherein the outer node is container-shaped and the inner node extends into the outer node, and wherein the first transistor is above the second transistor which in turn is above a semiconductor base.

4. The memory cell of claim 2 wherein the outer node is container-shaped and the inner node extends into the outer node, and wherein the second transistor is above the first transistor which in turn is above a semiconductor base.

5. The memory cell of claim 2 wherein:

the first transistor has a first source/drain region and a second source/drain region, and the outer node is electrically coupled with the first source/drain region;

the second transistor has a third source/drain region and a fourth source/drain region, and the inner second node is electrically coupled with the third source/drain region; and

the second and fourth source/drain regions are electrically coupled with first and second comparative bitlines, respectively.

6. The memory cell of claim 5 wherein the first comparative bitline is above the first transistor and the second comparative bitline is below the second transistor.

7. The memory cell of claim 6 being in a memory array; the first and second comparative bitlines being along a column of said memory array; the memory cell being one of a plurality of substantially identical memory cells between the first and second comparative bitlines along said column.

8. An apparatus comprising:

a semiconductor base;

an insulating film over the semiconductor base;

a memory array supported by the insulating film, and including a plurality of memory cells; each of the memory cells comprising:

a first transistor, a second transistor and a capacitor, with the capacitor being vertically disposed between the first transistor and the second transistor; the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor, the first node comprising vertical sidewalls, the second node extending along a portion of the vertical sidewalls, the portion being less than an entirety of the vertical sidewalls;

a plurality of pairs of bitlines;

a plurality of wordlines, each of the memory cells being coupled to an associated one individual of the plurality of pairs of bitlines and an associated one individual of the plurality of wordlines, an example one of the memory cells being coupled to an associated one of the plurality of pairs of bitlines and an associated one of the plurality of wordlines, the first and second transistors and the capacitor of the example one of the memory cells being coupled in series between the bitlines of the associated one of the plurality of pairs of bitlines;

wherein each of the memory cells comprises a first semiconductor post and a second semiconductor post; the first semiconductor post extending vertically through the first transistor to directly physically contact a first bitline and including the source/drain regions and a channel region of the first transistor, and the second semiconductor post extending vertically through the second transistor to directly physically contact a second bitline and including the source/drain regions and a channel region of the second transistor;

gate material extending vertically along the channel region on at least two opposing sides of each of the first and second semiconductor posts; and

wherein the first and second semiconductor posts are vertically aligned with each other between the first and second bitlines.