Memories and methods to provide configuration information to controllers

1. A memory module comprising:

a first three-dimensional memory package including at least two stacked memory dies, wherein the first three-dimensional memory package is configured to receive a first clock enable signal and a first plurality of chip select signals;

a second three-dimensional memory package including at least two stacked memory dies, wherein the second three-dimensional memory package is configured to receive a second clock enable signal and a second plurality of chip select signals; and

wherein the at least two stacked dies of the first three-dimensional memory package are assigned respective memory ranks that are different and non-consecutive relative to one another and the at least two stacked dies of the second three-dimensional memory package are assigned respective memory ranks that are different and non-consecutive relative to one another.

2. The memory module of claim 1 , further comprising:

a memory controller coupled to the first and second three-dimensional memory packages and configured to provide the first clock enable signal and the first plurality of chip select signals to the first three-dimensional memory package and provide the second clock enable signal and the second plurality of chip select signals to the second three-dimensional memory package.

3. The memory module of claim 2 , further comprising:

a signal presence detect unit configured to provide configuration data to the memory controller, wherein the configuration data is associated with a quad die package.

4. The memory module of claim 1 , wherein individual ones of the at least two stacked memory dies of the first three-dimensional memory package are configured to receive the first clock enable signal and individual ones of the at least two stacked memory dies of the second three-dimensional memory package are configured to receive the second clock enable signal.

5. The memory module of claim 1 , wherein each of the non-consecutive memory ranks of the at least two stacked dies of the first three-dimensional memory package and each of the non-consecutive memory ranks of the at least two stacked dies of the second three-dimensional memory package correspond to a respective rank of a memory package having at least four ranks, wherein, within the memory package having at least four ranks, at least one rank of the first three-dimensional memory package is consecutive with at least one rank of the second three-dimensional memory package.

6. The memory module of claim 5 , wherein a first memory die and a second memory die of the at least two stacked memory dies of the first three-dimensional memory package are coupled together and external signals for the second memory die are coupled through the first memory die, wherein the at least two stacked memory dies of the first three-dimensional memory package are each identified with a different memory rank.

7. The memory module of claim 6 , wherein the at least two stacked memory dies of the second three-dimensional memory package are each identified with a different memory rank.

8. An apparatus comprising:

a first three-dimensional memory package including a first memory die stacked on a second memory die, wherein the first memory die is identified with a first memory rank and the second memory die is identified with a second memory rank, wherein the first three-dimensional memory package is configured to receive a first clock enable signal, a first chip select signal, and a second chip select signal;

a second three-dimensional memory package including a third memory die stacked on a fourth memory die, wherein the third memory die is identified with a third memory rank and the fourth memory die is identified with a fourth memory rank, wherein the second three- dimensional memory package is configured to receive a second clock enable signal, a third chip select signal, and a fourth chip select signal; and

wherein the third memory rank assigned to the third memory die of the second three-dimensional memory package has a value that falls sequentially between a value of the first memory rank assigned to the first memory die of the first three-dimensional memory package and a value of the second memory rank assigned to the second memory die of the first three-dimensional memory package.

9. The apparatus of claim 8 , wherein the second memory rank assigned to the second memory die of the first three-dimensional memory package has a value that falls sequentially between the value of the third memory rank assigned to the third memory die of the second three-dimensional memory package and a value of the fourth memory rank assigned to the fourth memory die of the second three-dimensional memory package.

10. The apparatus of claim 8 , further comprising a signal presence detect unit configured to provide configuration data to a memory controller, wherein the configuration data includes control signal timings for accessing the first and second memory dies of the first three-dimensional memory package and the third and fourth memory dies of the second three-dimensional memory package.

11. The apparatus of claim 10 , wherein the control signal timings provided from the signal presence detection unit to the memory controller include timing relationships between clock enable signals received at the first and second three-dimensional memory packages, the first, second, third, and fourth chip select signals, and on-die termination signals received at the first and second three-dimensional memory packages.

12. The apparatus of claim 10 , wherein the signal presence detect unit is configured to provide the configuration data to the memory controller in response to receipt of a configuration signal.

13. The apparatus of claim 10 , wherein the signal presence detect unit is configured to provide the configuration data to the memory controller during initialization.

14. The apparatus of claim 10 , wherein the configuration data further includes data corresponding to input/output (I/O) pin assignments for the first clock enable signal, the first chip select signal, and the second chip select signal of the first three-dimensional memory package and I/O pin assignments for the second clock enable signal, the third chip select signal, and the fourth chip select signal of the second three-dimensional memory package.

15. A method comprising:

receiving a first clock enable signal and a first chip select signal at a first memory die of a first three-dimensional memory package of a memory module, wherein the first chip select signal has a value indicating selection of the first memory die for a first memory access operation, wherein the first memory die is identified with a first memory rank;

receiving a second clock enable signal and a second chip select signal at a second memory die of a second three-dimensional memory package of the memory module, wherein the second chip select signal has a value indicating selection of the second memory die for a second memory access operation, wherein the second memory die is identified with a second memory rank;

receiving the first clock enable signal and a third chip select signal at a third memory die of the first three-dimensional memory package, wherein the third chip select signal has a value indicating selection of the third memory die for a third memory access operation, wherein the third memory die is identified with a third memory rank; and

receiving the second clock enable signal and a fourth chip select signal at a fourth memory die of the second three-dimensional memory package, wherein the fourth chip select signal has a value indicating selection of the fourth memory die for a fourth memory access operation, wherein the fourth memory die is identified with a fourth memory rank, wherein the second memory rank assigned to the second memory die of the second three-dimensional memory package has a value that falls sequentially between a value of the first memory rank assigned to the first memory die of the first three-dimensional memory package and a value of the third memory rank assigned to the third memory die of the first three-dimensional memory package.

16. The method of claim 15 , further comprising providing configuration data to a memory controller from a signal presence detect unit of the memory module, wherein the configuration data includes data corresponding to input/output (I/O) pin assignments for the first clock enable signal, the first chip select signal, and the third chip select signal of the first three-dimensional memory package and I/O pin assignments for the second clock enable signal, the second chip select signal, and the fourth chip select signal of the second three-dimensional memory package.

17. The method of claim 15 , further comprising providing configuration data to a memory controller from a signal presence detect unit of the memory module, wherein the configuration data includes control signal timings for accessing the first and third memory dies of the first three-dimensional memory package and the second and fourth memory dies of the second three-dimensional memory package.

18. The method of claim 17 , wherein providing the configuration data to the memory controller includes providing timing relationships between clock enable signals received at the first and second three-dimensional memory packages, the first, second, third, and fourth chip select signals, and on-die termination signals received at the first and second three-dimensional memory packages.

19. The method of claim 17 , further comprising receiving a configuration signal, wherein provision of the configuration data to the memory controller is in response to receipt of the configuration signal.

20. The method of claim 15 , wherein the third memory die is stacked on the first memory die within the first three-dimensional memory package and the second memory die is stacked on the fourth memory die within the second three-dimensional memory package.