IP Library Granted Patent US 10,423,486
Granted Patent B2
US 10,423,486 · App. 16/212,513 · Granted Sep 24, 2019

Error code calculation on sensing circuitry

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Quick Facts
Patent No.
US 10,423,486
App. No.
16/212,513
Granted
Sep 24, 2019
Kind
B2
Abstract

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

Claims (34)

1. An apparatus comprising:

an array of memory cells that are coupled to sense lines; and

a controller configured to:

control a sensing circuitry that is coupled to the sense lines, to perform a number of operations without firing a column decode signal to:

calculate an error code for data stored in the array of memory cells; and

compare the error code with an initial error code for the data to determine whether the data has been modified.

2. The apparatus of claim 1 , wherein the controller is further configured to perform AND operations, OR operations, SHIFT operations, and INVERT operations without firing the column decode signal.

3. The apparatus of claim 1 , wherein the sensing circuitry comprises a sense amplifier and a compute component for each sensing component coupled to one of the sense lines.

4. The apparatus of claim 3 , wherein the sense amplifier further comprises a primary latch and the compute component comprises a secondary latch.

5. The apparatus of claim 1 , wherein the data comprises at least one of data and code storage.

6. The apparatus of claim 5 , wherein the code storage comprises an operating system.

7. The apparatus of claim 1 , wherein the controller is further configured to provide instructions to the sensing circuitry that enable the sensing circuitry to perform the number of operations.

8. A method, comprising:

controlling a sensing circuitry that is coupled to sense lines, to perform a number of operations without firing a column decode signal to:

calculate an error code for data stored in the array of memory cells; and

compare the error code with an initial error code for the data to determine whether the data has been modified.

9. The method of claim 8 , further comprising performing AND operations, OR operations, SHIFT operations, and INVERT operations without firing the column decode signal.

10. The method of claim 8 , further comprising providing instructions to the sensing circuitry that enable the sensing circuitry to perform the number of operations.

11. The method of claim 10 , further comprising repetitively providing the instructions to the sensing circuitry at a given interval of time.

12. The method of claim 8 , further comprising informing a host that the data has been modified.

13. A system comprising:

a host;

a memory device coupled to the host, the memory device including:

an array of memory cells that are coupled to sense lines; and

a controller configured to control a sensing circuitry that is coupled to the sense lines, to perform a number of operations without firing a column decode signal to:

calculate an error code for data stored in the array of memory cells; and

compare the error code with an initial error code for the data to determine whether the data has been modified.

14. The system of claim 13 , wherein the host is external to the memory device.

15. The system of claim 13 , wherein the host comprises a processor.

16. The system of claim 13 , wherein the host comprises one of the group of hosts including a laptop computer, a desktop computer, a digital camera, a smart phone, and a memory card reader.

17. The system of claim 13 , wherein the controller is further configured to perform AND operations, OR operations, SHIFT operations, and INVERT operations without firing the column decode signal.

18. The system of claim 13 , wherein the controller is further configured to provide instructions to the sensing circuitry that enable the sensing circuitry to perform the number of operations.

19. The system of claim 18 , wherein the controller is configured to inform the host that the data has been modified.

20. The system of claim 18 , wherein the controller is configured to repetitively provide the instructions to the sensing circuitry at a given interval of time.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2018
From: LEA, PERRY V.; FINKBEINER, TIMOTHY P.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047699/0061 →