IP Library Granted Patent US 10,636,678
Granted Patent B2
US 10,636,678 · App. 16/203,538 · Granted Apr 28, 2020

Semiconductor die assemblies with heat sink and associated systems and methods

Inventors: Wei Zhou (Singapore, SG); Zhaohui Ma (Singapore, SG); Aibin Yu (Singapore, SG)
Assignee: Micron Technology, Inc.
H01L21/4882H01L21/4878H01L21/561H01L21/565H01L21/568H01L21/78H01L23/3121H01L23/367H01L23/3731H01L23/3738H01L23/4334H01L24/17H01L24/92H01L24/94H01L24/97H01L25/0657H01L25/18H01L25/50H01L24/05H01L24/06H01L24/13H01L24/16H01L24/29H01L24/32H01L24/33H01L24/81H01L24/83H01L2224/0401H01L2224/06181H01L2224/13147H01L2224/16145H01L2224/16146H01L2224/16227H01L2224/17181H01L2224/17519H01L2224/293H01L2224/29191H01L2224/29393H01L2224/32145H01L2224/32225H01L2224/33181H01L2224/73204H01L2224/73253H01L2224/81H01L2224/83H01L2224/83104H01L2224/92125H01L2224/94H01L2224/97H01L2225/06513H01L2225/06517H01L2225/06541H01L2225/06565H01L2225/06568H01L2225/06589H01L2924/00H01L2924/00014H01L2924/014H01L2924/01006H01L2924/01014H01L2924/05432H01L2924/15311H01L2924/15738H01L2924/15787
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Quick Facts
Patent No.
US 10,636,678
App. No.
16/203,538
Granted
Apr 28, 2020
Kind
B2
Abstract

Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.

Claims (28)

1. A method of manufacturing a semiconductor die assembly, comprising:

providing a semiconductor wafer having a first side and a second side opposite the first side;

attaching a semiconductor die stack to the first side of the semiconductor wafer; and

forming a plurality of heat transfer features at the second side of the wafer, wherein the heat transfer features are defined by a plurality of grooves that define an exposed continuous surface of the semiconductor wafer at the second side compared to a planar surface of the semiconductor wafer.

2. The method of claim 1 , further comprising at least partially encapsulating the semiconductor die stack with a mold material.

3. The method of claim 2 , further comprising cutting through the semiconductor wafer and the mold material to singulate the semiconductor die stack.

4. The method of claim 1 wherein the plurality of heat transfer features extend along a first width of the semiconductor wafer, and wherein the semiconductor die stack includes a second width less than the first width.

5. The method of claim 1 , further comprising, before forming the plurality of heat transfer features, disposing a mold material over the semiconductor die stack and the first side of the wafer.

6. The method of claim 1 wherein forming the plurality of heat transfer features includes removing material from the semiconductor wafer at the second side.

7. The method of claim 1 , further comprising, before forming the plurality of heat transfer features, thinning the semiconductor wafer at the second side.

8. The method of claim 1 wherein the heat transfer features are first heat transfer features, the grooves are first grooves, and the semiconductor die stack includes an outermost surface, the method further comprising:

forming a plurality of second heat transfer features along a semiconductor blank attached to the outermost surface of the semiconductor die stack, wherein the second heat transfer features are defined by a plurality of second grooves that increase an exposed continuous surface of the semiconductor blank compared to a planar surface of the semiconductor blank.

9. The method of claim 8 , further comprising encapsulating the second heat transfer features in a mold material.

10. The method of claim 1 , wherein the semiconductor wafer includes peripheral portions that extend beyond a footprint of the semiconductor die stack.

11. A method of manufacturing a semiconductor die assembly, comprising:

providing a semiconductor wafer having a first side, a second side opposite the first side, and a plurality of first grooves extending from the first side to an intermediate depth of the semiconductor wafer;

attaching a plurality of semiconductor die stacks to the first side of the semiconductor wafer, wherein individual semiconductor die stacks are disposed between adjacent first grooves; and

forming a plurality of heat transfer features at the second side of the semiconductor wafer, wherein the heat transfer features are defined by a plurality of second grooves that define an exposed continuous surface of the semiconductor wafer at the second side compared to a planar surface of the semiconductor wafer.

12. The method of claim 11 , further comprising, before forming the plurality of heat transfer features, thinning the semiconductor wafer at the second side at least to the intermediate depth.

13. The method of claim 12 wherein thinning the semiconductor wafer comprises singulating the individual semiconductor die stacks from one another.

14. The method of claim 12 , further comprising, before thinning the wafer, disposing a mold material over the first side of the semiconductor wafer such that the semiconductor die stacks are encapsulated by the mold material.

15. The method of claim 14 , further comprising singulating the individual semiconductor die stacks from one another by cutting through the mold material and the semiconductor wafer.

16. The method of claim 11 , further comprising at least partially encapsulating the semiconductor die stack with a mold material.

17. The method of claim 16 , further comprising cutting through the semiconductor wafer and the mold material to singulate a semiconductor device including the individual semiconductor die stack and the cut semiconductor wafer.

18. The method of claim 11 wherein the heat transfer features are first heat transfer features and the individual semiconductor die stacks each include an outermost surface, the method further comprising:

forming a plurality of second heat transfer features along a semiconductor blank attached to the outermost surface of the semiconductor die stack, wherein the second heat transfer features are defined by a plurality of third grooves that increase an exposed continuous surface of the semiconductor blank compared to a planar surface of the semiconductor blank.

19. The method of claim 11 wherein the semiconductor wafer includes a first thickness, and wherein forming the plurality of heat transfer features includes removing material from the second side of the semiconductor wafer such that the heat transfer features extend a first distance through the wafer, the first distance being less than the first thickness.

20. The method of claim 11 wherein the individual semiconductor die stacks each include a plurality of semiconductor dies stacked in a first direction away from the semiconductor wafer, and wherein the heat transfer features face toward a second direction opposite the first direction.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2018
From: ZHOU, WEI; MA, ZHAOHUI; YU, AIBIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047613/0633 →
Cited By (1)
US 12,642,094