Circuits, apparatuses, and methods for frequency division

1. An apparatus comprising:

first and second power lines;

an output circuit;

a first circuit including a plurality of first transistors coupled between the first power line and the output circuit, the plurality of first transistors including a first enable circuit provided with a divide enable signal; and

a second circuit including a plurality of second transistors coupled between the output circuit and the second power line, the plurality of second transistors including a second enable circuit provided with the divide enable signal;

wherein the first circuit is configured to provide a first clock signal to the output circuit responsive to a reference clock signal and an active divide enable signal provided to the first enable circuit,

wherein the second circuit is configured to provide a second clock signal to the output circuit responsive to the reference clock signal and an inactive divide enable signal provided to the second enable circuit, and

wherein the first and second clock signals have a first frequency, and a second frequency that is different from the first frequency, respectively.

2. The apparatus of claim 1 , wherein each transistor of the plurality of first transistors is of a first conductivity type.

3. The apparatus of claim 2 , wherein each transistor of the plurality of second transistors is of a second conductivity type.

4. The apparatus of claim 1 , further comprising a third transistor coupled to the output circuit via a first node,

wherein output of the first circuit and output of the second circuit are coupled to the output circuit via the first node.

5. The apparatus of claim 1 , wherein:

gates of the plurality of first transistors are configured to input the divide enable signal and the reference clock signal, respectively, and

a frequency of the reference clock signal is the first frequency.

6. The apparatus of claim 5 , wherein:

the second circuit is configured to input a precharge signal and the reference clock signal, and

divide the first frequency of the reference clock signal to provide the second frequency.

7. The apparatus of claim 1 , further comprising:

a first frequency circuit including the plurality of first transistors; and

a second frequency circuit including the plurality of second transistors,

wherein a frequency of the reference clock signal is the first frequency,

wherein the first frequency circuit is configured to provide the first clock signal at the first frequency, and

wherein the second frequency circuit is configured to divide the first frequency to provide the second frequency, and provide the second clock signal at the second frequency.

8. The apparatus of claim 7 , wherein the first and second frequency circuits are configured to provide the first and second clock signals, respectively, with substantially a same propagation delay.

9. The apparatus of claim 1 , further comprising:

a first frequency circuit including the plurality of first transistors; and

a second frequency circuit including the plurality of second transistors,

wherein the first and second frequency circuits are configured to provide the first and second clock signals, respectively, with substantially a same propagation delay.

10. The apparatus of claim 1 , wherein one transistor of each of the plurality of first transistors and the plurality of second transistors is coupled to receive the reference clock signal,

wherein the plurality of first transistors are configured to be controlled to provide the first clock signal based on the reference clock signal received by the one transistor of the plurality of first transistors when enabled in a first operation mode, and

wherein the plurality of second transistors are configured to provide the second clock signal based on the reference clock signal received by the one transistor of the plurality of second transistors when enabled in a second operation mode.

11. An apparatus comprising:

a clock circuit including:

a first node configured to provide an output clock signal;

a pair of first transistors coupled to the first node and configured to be controlled by a first enable circuit provided with a divide enable signal and further configured to provide the output clock signal that has a first frequency responsive to an input clock signal and an active divide enable signal provided to the first enable circuit, and

a pair of second transistors coupled to the first node and configured to be controlled by a second enable circuit provided with the divide enable signal and further configured to provide the output clock signal that has a second frequency responsive to the input clock signal and an inactive divide enable signal provided to the second enable circuit, wherein the second frequency is lower than the first frequency.

12. The apparatus of claim 11 , wherein each transistor of the pair of first transistors is of a first conductivity type, and each transistor of the pair of second transistors is of a second conductivity type.

13. The apparatus of claim 11 , wherein a gate of one transistor of the pair of first transistors is configured to receive the input clock signal, and

wherein the pair of first transistors are configured to be controlled to provide the output clock signal at the first frequency based on the received input clock signal in a first operation mode.

14. The apparatus of claim 13 , wherein a gate of one transistor of the pair of second transistors is configured to receive the input clock signal, and

wherein the pair of second transistors are configured to be controlled to provide the output clock signal at the second frequency based on the received input clock signal in a second operation mode.

15. The apparatus of claim 11 , further comprising a third transistor coupled to the first node.

16. The apparatus of claim 15 , wherein a gate of one transistor of the pair of second transistors is coupled to a second node, and the gate of the one transistor of the pair of second transistors is configured to input a precharge signal via the second node, and

wherein a gate of the third transistor is coupled to the second node, and the gate of the third transistor is configured to input the precharge signal via the second node.

17. An apparatus comprising:

a clock circuit including:

first and second power lines;

a first node configured to provide an output clock signal;

first and second transistors coupled to the first node and configured to be controlled by a first enable circuit provided with a divide enable signal and further configured to provide the output clock signal that has a first frequency responsive to an input clock signal and an active divide enable signal provided to the first enable circuit, wherein a first frequency circuit including the first and second transistors is configured to operate at the first frequency in a first operation mode; and

third and fourth transistors coupled to the first node and configured to be controlled by a second enable circuit provided with the divide enable signal and further configured to provide the output clock signal that has a second frequency responsive to the input clock signal and an inactive divide enable signal provided to the second enable circuit, wherein a second frequency circuit including the third and fourth transistors is configured to operate at the second frequency in a second operation mode, and

wherein the first frequency is equal to a frequency of the input clock signal and the second frequency is different from the first frequency.

18. The apparatus of claim 17 , wherein the second frequency is lower than the first frequency.

19. The apparatus of claim 17 , wherein the first transistor is configured to be rendered conductive in the first operation mode and non-conductive in the second operation mode.