Apparatuses and methods for memory operations having variable latencies

1. A method, comprising:

storing in a register a maximum variable latency period for write operations and a maximum variable latency period for read operations:

receiving, at a memory, memory instructions and addresses associated with the memory instruction; and

responsive to the received memory instructions and prior to receiving write data or providing read data associated with the memory instruction, providing a first data signal indicative of an end of a variable latency period and providing a second data signal concurrently with providing the first data signal, wherein the second data signal includes information related to an acceptance of the memory instruction.

2. The method of claim 1 , wherein the memory instructions and addresses associated with the memory instruction are received concurrently.

3. The method of claim 1 ; wherein the variable latency period for the memory instruction is based at least in part on a current memory operation and the memory instruction.

4. The method of claim 1 , wherein the memory instructions comprise a plurality of write instructions, and the method further comprises:

storing write data for the plurality of write instructions in a write data buffer; and

responsive to a last write instruction, writing the write data for the plurality of write instructions stored in the write buffer to the memory.

5. The method of claim 1 further comprising waiting a bus turnaround time following an acknowledgement before providing data associated with a write instruction.

6. The method of claim 5 , wherein the acknowledgment is represented by the first data signal changing from a first logic level to a second logic level.

7. The method of claim 1 further comprising waiting a bus turnaround time following the addresses associated with the memory instruction.

8. The method of claim 1 further comprising:

waiting a bus turnaround time after receiving the addresses.

9. A method; comprising:

providing a memory instruction and an address to a memory; and

prior to exchanging read or write data associated with the memory instruction with the memory:

receiving a first signal from the memory indicative of an end of a variable latency period for the memory instruction, wherein the variable latency period is based, at least in part on a value of a maximum variable latency period stored in a register of the memory, wherein the value of the maximum variable latency period is different for different types of memory instructions; and

receiving a second signal from the memory concurrently with receiving the first signal, wherein the second signal includes information related to acceptance of the memory instruction by the memory.

10. The method of claim 9 , wherein the second signal is represented by a combination of logic states of a plurality of signals.

11. The method of claim 9 , wherein exchanging data associated with the memory instruction with the memory occurs a bus turnaround time after receiving the second signal for a write instruction.

12. The method of claim 9 further comprising keeping a system bus busy until completion of a memory operation as represented by the received second signal.

13. The method of claim 9 further comprising aborting a memory operation related to the memory instruction to free a system bus and retrying the memory operation again at a later time.

14. A method, comprising:

storing in a register a maximum variable latency period for write operations and a maximum variable latency period for read operations;

receiving at a memory a write instruction and an address to which write data is to be written;

responsive to the received write instruction and prior to receiving the write data for the write instruction:

providing a first data signal to a memory controller coupled to the memory on a data bus to indicate an end of a variable latency period;

providing a second data signal to the memory controller on the data bus concurrently with providing the first data signal, wherein the second data signal represents additional information;

waiting a bus turnaround time after an acknowledgment; and

receiving the write data for the write instruction.

15. The method of claim 14 , wherein the acknowledgment is represented by the first data signal changing from a first logic level to a second logic level.

16. The method of claim 14 further comprising:

performing a write operation for the write instruction; and

suspending the write operation responsive to receiving a read instruction during the write operation.

17. The method of claim 14 further comprising:

storing the write data received for the write instruction in a write data buffer.

18. The method of claim 14 , wherein the write data for the write instruction is received after the acknowledgment and after the bus turnaround time.

19. The method of claim 14 further comprising:

performing a write operation responsive to receiving the write instruction; and

writing write data to memory that are stored in a write data buffer.

20. The method of claim 17 wherein the write data that are stored in the write data buffer is associated with a plurality of write instructions and the write operation is performed responsive to a last write instruction of the plurality of write instructions.