Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.
1. A processing system comprising:
a processor;
an imaging device coupled to the processor, the imaging device having a plurality of pixel cells, wherein at least one of the pixel cells comprises:
a semiconductor substrate including a strained silicon layer at an upper portion of the semiconductor substrate,
a photosensor for generating charge formed in an upper region of the semiconductor substrate, wherein the photosensor comprises a photosensitive region buried at least in part within the semiconductor substrate and separated from the strained silicon layer by an intermediary portion of the semiconductor substrate; and
a readout circuit comprising at least one output transistor formed on the semiconductor substrate.
2. The system of claim 1 , wherein the strained silicon layer has a thickness of about 500 Å to about 1000 Å.
3. The system of claim 1 , wherein the strained silicon layer comprises a top silicon layer formed over a silicon-germanium layer.
4. The system of claim 3 , wherein the silicon-germanium layer is graded.
5. The system of 3 , wherein the silicon-germanium layer has a germanium concentration of about 30% to about 40%.
6. The system of claim 1 , wherein the intermediary portion comprises an undoped portion of the semiconductor substrate.
7. The system of claim 1 , wherein the photosensor is buried entirely below the strained silicon layer.
8. The system of claim 1 , wherein—
the at least one of the pixel cells further comprises a floating diffusion region; and
the at least one output transistor formed on the substrate is a reset transistor connected to the floating diffusion region for resetting the charge on the floating diffusion region.
9. The system of claim 8 , wherein the readout circuit further comprises:
a transfer transistor (1) formed on the substrate and (2) connected to the photosensor and the floating diffusion region for transferring charge from the photosensor to the floating diffusion region,
a source-follower transistor having a gate for receiving charge from the floating diffusion region, and
a row select transistor connected to the source-follower transistor for outputting a signal produced by the source-follower transistor.
10. A processing system comprising:
a processor; and
a plurality of pixel cells operably connected to the processor, each pixel cell comprising—
a semiconductor substrate including a strained silicon layer at an upper portion of the semiconductor substrate, and
a photosensor for generating charge formed in an upper region of the semiconductor substrate, wherein the photosensor comprises a photosensitive region buried at least in part within the semiconductor substrate and separated from the strained silicon layer by an intermediary portion of the semiconductor substrate,
wherein the processor is configured to (i) form and output a digital image based at least in part on the generated charge or (ii) process the digital image output from an imaging device comprising the plurality of pixel cells.
11. The system of claim 10 , wherein the strained silicon layer has a thickness of about 500 Å to about 1000 Å.
12. The system of claim 10 , wherein the strained silicon layer comprises a top silicon layer formed over a silicon-germanium layer.
13. The system of 12 , wherein the first silicon-germanium layer has a germanium concentration of about 30% to about 40%.
14. The system of claim 12 , wherein the silicon-germanium layer is graded.
15. The system of claim 12 , wherein the silicon-germanium layer is a first silicon-germanium layer, and wherein the strained silicon layer further comprises a second silicon-germanium layer between the top silicon layer and the first silicon-germanium layer.
16. The system of claim 10 , wherein the intermediary portion comprises an undoped portion of the semiconductor substrate.