Time-based access of a memory cell
View Patent ↗Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
1. A method, comprising:
sensing a first state of a ferroelectric capacitor in a ferroelectric memory cell;
sensing a second state of the ferroelectric capacitor different from the first state;
activating at least two latches based at least in part on a voltage level of a node different from a digit line satisfying a voltage threshold; and
identifying a logic state of the ferroelectric memory cell from at least three logic states based at least in part on the first state and the second state.
2. The method of claim 1 , wherein the first state of the ferroelectric capacitor is associated with a polarization of the ferroelectric capacitor.
3. The method of claim 1 , wherein the second state of the ferroelectric capacitor is associated with a dielectric charge stored on the ferroelectric capacitor.
4. The method of claim 1 , further comprising:
identifying a first bit of the logic state based at least in part on the first state; and
identifying a second bit of the logic state based at least in part on the second state.
5. The method of claim 1 , further comprising:
applying a first time-varying signal to one of the at least two latches; and
applying a second time-varying signal different from the first time-varying signal to another of the at least two latches,
wherein the logic state is identified based at least in part on values of the first time-varying signal and the second time-varying signal when activating the at least two latches.
6. The method of claim 1 , further comprising:
identifying a duration for a first voltage level of the digit line to satisfy the voltage threshold during an access operation, the duration based at least in part on the first state of the ferroelectric capacitor, the second state of the ferroelectric capacitor, and a voltage applied to the digit line.
7. The method of claim 1 , further comprising:
identifying a duration for a second voltage level of the node different from the digit line to satisfy the voltage threshold, the duration based at least in part on the first state of the ferroelectric capacitor and the second state of the ferroelectric capacitor.
8. A method, comprising:
sensing a first state associated with a ferroelectric capacitor of a ferroelectric memory cell;
sensing a second state associated with a middle electrode positioned between the ferroelectric capacitor and a selection component of the ferroelectric memory cell;
activating at least two latches based at least in part on a voltage level of a node different from a digit line satisfying a voltage threshold; and
identifying a logic state stored in the ferroelectric memory cell based at least in part on sensing the first state associated with the ferroelectric capacitor and sensing the second state associated with the middle electrode.
9. The method of claim 8 , wherein the first state comprises a polarization state of the ferroelectric capacitor.
10. The method of claim 8 , wherein the second state comprises a dielectric charge stored on the middle electrode.
11. The method of claim 8 , wherein identifying the logic state further comprises:
identifying a first bit of the logic state based at least in part on the first state; and
identifying a second bit of the logic state based at least in part on the second state.
12. The method of claim 8 , wherein the voltage threshold is associated with an expected upper-bound voltage stored in the middle electrode.
13. The method of claim 8 , further comprising:
applying a first time-varying signal to a first latch of the at least two latches; and
applying a second time-varying signal to a second latch of the at least two latches,
wherein the logic state is identified based at least in part on values of the first time-varying signal and the second time-varying signal when activating the at least two latches.
14. The method of claim 8 , further comprising:
identifying a second voltage level of the digit line during an access operation, the second voltage level based at least in part on the first state associated with the ferroelectric capacitor, the second state associated with the middle electrode, and a third voltage applied to the digit line.
15. The method of claim 8 , further comprising:
identifying a duration for a second voltage level of the node different than the digit line to satisfy the voltage threshold, the second voltage level based at least in part on the first state associated with the ferroelectric capacitor and the second state associated with the middle electrode.
16. An apparatus, comprising:
a ferroelectric memory cell comprising a ferroelectric capacitor;
a controller coupled to the ferroelectric memory cell and configured to:
sense a polarization state of the ferroelectric memory cell;
sense a dielectric charge state of the ferroelectric memory cell;
apply a first time-varying signal to a first latch;
apply a second time-varying signal different from the first time-varying signal to a second latch; and
identify a logic state of the ferroelectric memory cell from at least three logic states based at least in part on the polarization state, the dielectric charge state, and values of the first time-varying signal and the second time-varying signal when the first latch and the second latch are activated.
17. The apparatus of claim 16 , wherein the controller is further configured to:
identify a first bit of the logic state based at least in part on the polarization state; and
identify a second bit of the logic state based at least in part on the dielectric charge state, wherein identifying the logic state is based at least in part on identifying the first bit and identifying the second bit.