Ground reference scheme for a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.
1. A method, comprising:
applying a first voltage to a memory cell that is in electronic communication with a digit line; and
applying a second voltage to the memory cell after a rate of change of a voltage of the digit line has reached a threshold in response to the first voltage being applied.
2. The method of claim 1 , further comprising:
determining that the rate of change of the voltage of the digit line has reached the threshold after the first voltage is applied.
3. The method of claim 1 , further comprising:
determining that the rate of change of the voltage of the digit line has reached the threshold based at least in part on the voltage of the digit line being within a percent range of an expected settling voltage; and
applying the second voltage based at least in part on determining that the rate of change of the voltage of the digit line has reached the threshold.
4. The method of claim 3 , wherein the expected settling voltage is associated with experimental data for the memory cell, a prediction model for the memory cell, or a combination thereof.
5. The method of claim 1 , further comprising:
determining that the rate of change of the voltage of the digit line has reached the threshold based at least in part on a duration after applying the first voltage having elapsed; and
applying the second voltage based at least in part on determining that the rate of change of the voltage of the digit line has reached the threshold.
6. The method of claim 5 , wherein the duration is associated with a characteristic of a ferroelectric capacitor of the memory cell, a characteristic of the digit line, a timing associated with reading or writing to the memory cell, or a combination thereof.
7. The method of claim 1 , further comprising:
determining that the rate of change of the voltage of the digit line has reached the threshold based at least in part on the voltage associated with the digit line reaching a voltage threshold; and
applying the second voltage based at least in part on determining that the rate of change of the voltage of the digit line has reached the threshold.
8. The method of claim 1 , wherein the first voltage and the second voltage have opposite polarities.
9. A method, comprising:
releasing charge to a digit line that is in electronic communication with a memory cell;
removing charge from the digit line based at least in part on determining that a rate of change of an electrical characteristic of the digit line has reached a threshold in response to releasing the charge; and
performing a sensing operation of the digit line after removing the charge.
10. The method of claim 9 , wherein performing the sensing operation comprises:
latching an output of a sense component based at least in part on a relationship between the electrical characteristic of the digit line and a reference electrical characteristic associated with a virtual ground.
11. The method of claim 10 , wherein releasing the charge to the digit line comprises:
releasing a first amount of charge if the memory cell is associated with a first memory state and releasing a second amount of charge if the memory cell is associated with a second memory state.
12. The method of claim 9 , wherein the electrical characteristic comprises a voltage.
13. The method of claim 9 , wherein the memory cell comprises a ferroelectric memory cell, and wherein the ferroelectric memory cell comprises a ferroelectric capacitor in electronic communication with the digit line.
14. The method of claim 13 , wherein the ferroelectric capacitor is a source of at least a portion of the released charge, and wherein the ferroelectric capacitor is a sink of at least a portion of the removed charge.
15. An electronic memory apparatus, comprising:
a memory cell in electronic communication with a digit line;
a controller in electronic communication with the memory cell and operable to:
connect a first voltage source to the memory cell; and
connect a second voltage source to the memory cell after determining that a rate of change of the voltage of the digit line has reached a threshold.
16. The electronic memory apparatus of claim 15 , wherein the controller is further operable to:
determine that the rate of change of the voltage of the digit line has reached a threshold.
17. The electronic memory apparatus of claim 15 , further comprising:
a sense component; and
a reference digit line in electronic communication with the sense component and a switching component associated with a virtual ground.
18. The electronic memory apparatus of claim 17 , wherein the controller is further operable to:
latch an output of the sense component based at least in part on a relationship between the voltage of the digit line and a voltage of the reference digit line.
19. The electronic memory apparatus of claim 18 , wherein the voltage of the reference digit line is equal to a voltage of the virtual ground.
20. The electronic memory apparatus of claim 15 , wherein a voltage of the first voltage source is positive and a voltage of the second voltage source is negative.