IP Library Granted Patent US 10,884,661
Granted Patent B2
US 10,884,661 · App. 16/207,453 · Granted Jan 5, 2021

Command queuing

Inventors: Victor Y. Tsai (Palo Alto, CA); Danilo Caraccio (Buonalbergo, IT); Daniele Balluchi (Cernusco sul Naviglio, IT); Neal A. Galbo (Boca Raton, FL); Robert Warren (Loveland, CO)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/061G06F3/0611G06F3/0679G06F3/0688
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Quick Facts
Patent No.
US 10,884,661
App. No.
16/207,453
Granted
Jan 5, 2021
Kind
B2
Abstract

The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Claims (36)

1. A method for command queuing, comprising:

receiving a command at a memory system from a host, wherein the command includes a command descriptor block;

placing, in response to receiving the command descriptor block, the command described by the command descriptor block in a command queue of the memory system, wherein the command received from the host on a command line is added to the command queue of the memory system while a different command that was previously received from the host and added to the command queue is concurrently being executed in the memory system on a data bus;

changing the memory system from a Receiving Data state to a Transfer state in response to receiving, from the host, data corresponding to a receive data command; and

changing the memory system from a Sending Data state to the Transfer state in response to transferring, to the host, data corresponding to a send data command from the host, wherein a queue busy bit sent from the memory system to the host while the memory system is in the Transfer state indicates whether the memory system is ready to receive commands from the host.

2. The method of claim 1 , wherein the command descriptor block includes priority information for the command.

3. The method of claim 2 , wherein the priority information includes a parameter that indicates the command is placed in the command queue with highest priority for execution.

4. The method of claim 2 , wherein the priority information includes a parameter that indicates the command is placed in the command queue with chronological priority for execution.

5. The method of claim 2 , wherein the priority information includes a parameter that indicates the command is placed in the command queue without priority for execution.

6. The method of claim 1 , wherein the command descriptor block for the command includes a command operation code, priority information, a task tag, a command argument, a starting address, and a block count.

7. The method of claim 1 , wherein the method includes receiving the command at the memory system when the memory system is in the Transfer state.

8. The method of claim 1 , wherein the method includes command queuing using an embedded MultiMediaCard (e.MMC) protocol.

9. The method of claim 1 , wherein the method includes executing the command by receiving a ready to transfer command at the memory system from the host.

10. An apparatus, comprising:

a controller; and

a memory device coupled to the controller, wherein the apparatus is configured to:

place a command in a command queue in response to receiving the command that includes a command descriptor block, wherein the command received from a host on a command line is added to the command queue of a memory system while a different command that was previously received from the host and added to the command queue is concurrently being executed in the memory system on a data bus;

execute the command in response to receiving a ready to transfer command;

change the memory system from a Receiving Data state to a Transfer state in response to receiving, from the host, data corresponding to a receive data command; and

change the memory system from a Sending Data state to the Transfer state in response to transferring, to the host, data corresponding to a send data command from the host, wherein a queue busy bit sent from the memory system to the host while the memory system is in the Transfer state indicates whether the memory system is ready to receive commands from the host.

11. The apparatus of claim 10 , wherein apparatus is configured to execute the command by receiving a receive data command at the controller from the host, transitioning from the Transfer state to the Receiving Data state, and receiving data at the apparatus from the host.

12. The apparatus of claim 10 , wherein apparatus is configured to execute the command by receiving the send data command at the controller from the host, transitioning from the Transfer state to the Sending Data state, and sending data from the memory device to the host.

13. The apparatus of claim 10 , wherein the apparatus is configured to receive a task management function request command from the host and send a status of each of a number of commands in the command queue to the host.

14. The apparatus of claim 10 , wherein the apparatus is configured to receive a task management function request command from the host and abort each of a number of commands in the command queue.

15. A method for command queuing, comprising:

receiving a first command at a memory system from a host on a command line, wherein the first command includes a first command descriptor block;

placing, in response to receiving the first command descriptor block, the first command in a command queue of the memory system;

executing the first command in response to receiving a ready to transfer command;

receiving a second command at the memory system from the host on the command line, wherein the second command includes a second command descriptor block;

placing, in response to receiving the second command descriptor block, the second command in the command queue of the memory system while concurrently executing the first command on a data bus;

changing the memory system from a Receiving Data state to a Transfer state in response to receiving, from the host, data corresponding to a receive data command; and

changing the memory system from a Sending Data state to the Transfer state in response to transferring, to the host, data corresponding to a send data command from the host, wherein a queue busy bit sent from the memory system to the host while the memory system is in the Transfer state indicates whether the memory system is ready to receive commands from the host.

16. The method of claim 15 , further including interrupting the execution of the first command and executing the second command in response to the second command being placed in the command queue with a parameter that indicates the second command is placed in the command queue with highest priority for execution.

17. The method of claim 15 , wherein the method includes executing the second command by receiving a ready to transfer command at the memory system from the host and sending a data transfer request from the memory system to the host in response to receiving the ready to transfer command, wherein the data transfer request includes a data packet with information allowing for command execution on the host and memory system.

18. The method of claim 15 , wherein the method includes receiving the second command at the memory system from the host on a command line while the first number of command is being executed via data transfers on a data bus.

19. The method of claim 15 , the method includes resuming execution of the first command after execution of the second command has commenced.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 064905/0565 →
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2018
From: TSAI, VICTOR Y.; CARACCIO, DANILO; BALLUCHI, DANIELE; GALBO, NEAL A.; WARREN, ROBERT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047657/0102 →
Continuity (3)
Continuation 15246735 · Aug 25, 2016
Continuation 14181089 · Feb 14, 2014
Related Publication 20190102112A1 · Apr 4, 2019