IP Library Granted Patent US 10,146,477
Granted Patent B2
US 10,146,477 · App. 15/246,735 · Granted Dec 4, 2018

Command queuing

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Quick Facts
Patent No.
US 10,146,477
App. No.
15/246,735
Granted
Dec 4, 2018
Kind
B2
Abstract

The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Claims (33)

1. A method for command queuing in a computing system, comprising:

receiving a first queued command request at a memory system from a host, wherein the first queued command request indicates to the memory system that the host would like to send a command from the host to the memory system to add to a command queue of the memory system;

sending a first command response from the memory system to the host that indicates the memory system is not ready to receive the command in the command queue of the memory system;

receiving a task management function request command from the host;

sending a status of each of the commands in the command queue to the host in response to receiving the task management function request command;

receiving a second queued command request at the memory system from the host;

sending a second command response from the memory system to the host that indicates the memory system is ready to receive the command in the command queue of the memory system; and

receiving, in response to sending the second command response, a command descriptor block for the command at the memory system from the host; and

placing, in response to receiving the command descriptor block, the command described by the command descriptor block in the command queue of the memory system.

2. The method of claim 1 , wherein the command descriptor block includes priority information for the command.

3. The method of claim 2 , wherein the priority information includes a parameter that indicates the command is placed in the command queue with highest priority for execution.

4. The method of claim 2 , wherein the priority information includes a parameter that indicates the command is placed in the command queue with chronological priority for execution.

5. The method of claim 2 , wherein the priority information includes a parameter that indicates the command is placed in the command queue without priority for execution.

6. The method of claim 1 , wherein the command descriptor block for the command includes a command operation code, priority information, a task tag, a command argument, a starting address, and a block count.

7. The method of claim 1 , wherein the method includes receiving the queued command request at the memory system when the memory system is in a Transfer state.

8. The method of claim 1 , wherein the method includes changing the memory system from a Transfer state to a Receiving state in response to sending the command response.

9. The method of claim 1 , wherein the method includes command queuing using an embedded MultiMediaCard (e.MMC) protocol.

10. The method of claim 1 , wherein the method includes executing the command by receiving a ready to transfer commands at the memory system from the host.

11. A method for command execution in a memory system, comprising:

receiving a first number of queued command requests at a memory system from a host, wherein the first number of queued command requests indicate to the memory system that the host is ready to send a first number of commands for the memory system to include in a command queue in the memory system;

placing the first number of commands in a command queue in the memory system in response to receiving the first number of queued command requests; and

executing one of the first number of commands in the command queue on the memory system by receiving a ready to transfer command at the memory system from a host, wherein the ready to transfer command indicates the host is ready to transmit or receive data; sending a first data transfer request from the memory system to the host in response to receiving the ready to transfer command, wherein the first data transfer request indicates the memory system is not ready to send or receive data; and sending a second data transfer request from the memory system to the host in response to receiving the ready to transfer command, wherein the second data transfer request includes a data packet with information, including a direction of transfer bit, allowing for command execution of the command in the command queue by the host and memory system.

12. The method of claim 11 , wherein executing the command includes receiving a receive data command at the memory system from the host when the command is a write command.

13. The method of claim 12 , wherein, in response to receiving the receive data command from the host, the memory system transitions to a Receive state and the host sends data to the memory system.

14. The method of claim 11 , wherein executing the command includes receiving a send data command at the memory system from the host when the command is a read command.

15. The method of claim 14 , wherein, in response to receiving the send data command from the host, the memory system transitions to a Sending Data state and the memory system sends data to the host.

16. A method for command execution in a memory system, comprising:

executing a first number of commands in a command queue on the memory system by receiving a first number of ready to transfer commands at the memory system from a host and sending a first number of data transfer requests from the memory system to the host in response to receiving the first number of ready to transfer commands, wherein a first portion of the first number of data transfer requests indicate the memory system is not ready to send or receive data and a second portion of the first number of data transfer requests each includes a data packet with information, including a direction of transfer bit, allowing for command execution of commands in the command queue by the host and memory system; and

interrupting the execution of the first number of commands and executing a command from a second number of commands in response to the command from the second number of commands being placed in the command queue with a parameter that indicates the command is placed in the command queue with highest priority for execution.

17. The method of claim 16 , wherein the method includes executing the command from the second number of commands by receiving a ready to transfer command at the memory system from the host and sending a data transfer request from the memory system to the host in response to receiving the ready to transfer command, wherein the data transfer request includes a data packet with information allowing for command execution on the host and memory system.

18. The method of claim 16 , wherein the method includes receiving the second number of a queued command requests at the memory system from the host on a command line while at least a portion of the first number of commands are being executed via data transfers on a data bus.

19. The method of claim 16 , the method includes executing two or more of the first number of commands concurrently.

20. The method of claim 16 , the method includes resuming execution of the first number of commands after execution of the command from the second number of commands has commenced.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 064905/0565 →
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2016
From: TSAI, VICTOR Y.; CARACCIO, DANILO; BALLUCHI, DANIELE; GALBO, NEAL A.; WARREN, ROBERT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039538/0647 →