Patent Assignment
Reel/Frame 051028/0001
Release of Security Interest
Recorded: 2019-11-12
Received: 2019-11-12
Pages: 834
Assignor
JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Executed: 2019-07-31
Assignees
MICRON TECHNOLOGY, INC.
8000 S FEDERAL WAY, BOISE, ID, 83707, UNITED STATES
MICRON SEMICONDUCTOR PRODUCTS, INC.
8000 S FEDERAL WAY, BOISE, ID, 83707, UNITED STATES
Covered Properties
(100)
Methods Used In Forming An Array Of Elevationally-Extending Strings Of Memory Cells, Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells, And Methods Of Forming An Array Of Vertical Strings Of Memory Cells
Application:
16/111,584 →
Longest Element Length Determination in Memory
Application:
16/039,443 →
Static Identifications in Object-based Memory Access
Application:
16/028,840 →
Securing Conditional Speculative Instruction Execution
Application:
16/028,750 →
Integrated Assemblies Having Bitline Contacts
Application:
16/010,779 →
Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch Different from the First Pitch, and Methods of Forming Integrated Assemblies
Application:
16/010,734 →
Downloading System Memory Data in Response to Event Detection
Application:
16/010,646 →
Translation Lookaside Buffer in a Switch
Application:
16/009,335 →
Detecting Road Conditions Based on Braking Event Data Received from Vehicles
Application:
16/010,060 →
Apparatuses and Method for Reducing Sense Amplifier Leakage Current During Active Power-Down
Application:
16/009,806 →
Methods of Operating Memory
Application:
16/009,541 →
Electronic Device with a Reconfigurable Charging Mechanism
Application:
16/009,128 →
Memory Device with Dynamic Program-Verify Voltage Calibration
Application:
16/009,091 →
Etched Trenches in Bond Materials for Die Singulation, and Associated Systems and Methods
Application:
16/008,836 →
Color Filter Array, Imagers and Systems Having Same, and Methods of Fabrication and Use Thereof
Application:
16/009,137 →
Reduced Voltage Nonvolatile Flash Memory
Application:
16/008,480 →
Apparatuses and Methods for Identifying Memory Devices of a Semiconductor Device Sharing an External Resistance
Application:
16/008,955 →
Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of Vertically Opposed Capacitors
Application:
16/008,942 →
Semiconductor Device with a Multi-Layered Encapsulant and Associated Systems, Devices, and Methods
Application:
16/009,119 →
Sense Amplifier Constructions
Application:
16/007,022 →
Transistors
Application:
16/007,139 →
Methods of Sealing Openings, and Methods of Forming Integrated Assemblies
Application:
16/007,361 →
Health Characteristics of a Memory Device
Application:
16/007,191 →
Generating and Using Invertible, Shortened Bose-Chaudhuri-Hocquenghem Codewords
Application:
16/007,806 →
3D Interconnect Multi-Die Inductors with Through-Substrate via Cores
Application:
16/007,824 →
Memory Cell And An Array Of Memory Cells
Application:
16/007,054 →
Semiconductor Devices with Package-Level Configurability
Application:
16/007,903 →
Multi-Die Inductors with Coupled Through-Substrate via Cores
Application:
16/007,670 →
Methods of Forming a Semiconductor Device Comprising First and Second Nitride Layers
Application:
16/006,603 →
Shifting Data
Application:
16/006,514 →
Memory Cells and Memory Arrays
Application:
16/006,301 →
Semiconductor Device Assemblies with Lids Including Circuit Elements
Application:
16/006,746 →
Semiconductor Device Assemblies with Annular Interposers
Application:
16/006,679 →
Memory Devices Configured to Latch Data for Output in Response to an Edge of a Clock Signal Generated in Response to an Edge of Another Clock Signal
Application:
16/006,192 →
Magnetic Tunnel Junctions
Application:
16/006,588 →
Apparatuses and Methods for Memory Including Ferroelectric Memory Cells and Dielectric Memory Cells
Application:
16/005,493 →
Processing in Memory (Pim) Capable Memory Device Having Timing Circuitry to Control Timing of Operations
Application:
16/004,864 →
Encryption of Executables in Computational Memory
Application:
16/004,663 →
Semiconductor Devices and Structures
Application:
16/004,908 →
Memory as a Programmable Logic Device
Application:
16/003,357 →
Methods of Forming a Self-Assembled Block Copolymer Material
Application:
16/004,063 →
Integrated Assemblies Comprising Stud-Type Capacitors
Application:
16/003,571 →
Accessing Data in Memory
Application:
16/004,122 →
Methods of Forming Integrated Assemblies Having Dielectric Regions Along Conductive Structures
Application:
16/002,890 →
Stacked Semiconductor Die Assemblies with High Efficiency Thermal Paths and Molded Underfill
Application:
16/002,843 →
Dynamic Line Width Memory Cache Systems and Methods
Application:
62/682,050 →
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge Storage Transistor And Arrays Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge Storage Transistor
Application:
16/002,129 →
Image Processor Formed in an Array of Memory Cells
Application:
16/002,644 →
Integrated Circuitry
Application:
16/002,162 →
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells, Methods Of Forming Polysilicon, Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor, And Electronic Components Comprising Polysilicon
Application:
16/002,075 →
Weight Storage Using Memory Device
Application:
16/001,790 →
Techniques for Programming Multi-Level Self-Selecting Memory Cell
Application:
16/001,798 →
Fabrication of Electrodes for Memory Cells
Application:
16/001,795 →
Methods and Apparatuses of Driver Circuits Without Voltage Level Shifters
Application:
16/001,743 →
Array Plate Short Repair
Application:
16/001,784 →
Memories Including Multiple Arrays of Non-Volatile Memory Cells Selectively Connected to Sense Circuitry Using Different Numbers of Data Lines
Application:
16/001,387 →
Methods of Forming Integrated Structures
Application:
15/997,992 →
Apparatuses and Methods for Providing Constant Current
Application:
16/000,220 →
Forming Conductive Plugs for Memory Device
Application:
16/000,697 →
Methods of Forming Magnetic Memory Cells and Semiconductor Devices
Application:
16/000,272 →
Apparatuses and Methods for Adjusting Delay of Command Signal Path
Application:
16/000,149 →
Systems and Methods for a Centralized Command Address Input Buffer
Application:
15/997,356 →
Device Having Multiple Channels with Calibration Circuit Shared by Multiple Channels
Application:
15/997,417 →
Simulating Access Lines
Application:
15/997,389 →
Semiconductor Constructions, and Semiconductor Processing Methods
Application:
15/995,648 →
Event Logging in a Multi-Core System
Application:
15/996,319 →
Integrated Circuitry, Memory Integrated Circuitry, And Methods Used In Forming Integrated Circuitry
Application:
15/995,475 →
Dynamic Allocation of Volatile Memory to Storage Management Components of a Non-Volatile Storage Device
Application:
15/996,303 →
Using Counters to Efficiently Track Busy Time of Storage Systems
Application:
15/996,287 →
Devices Including Memory Arrays, Row Decoder Circuitries and Column Decoder Circuitries
Application:
15/995,626 →
Apparatuses and Methods for Random Number Generation
Application:
15/995,748 →
Data Relocation in Memory Having Two Portions of Data
Application:
15/994,477 →
Apparatuses, Multi-Chip Modules and Capacitive Chips
Application:
15/994,807 →
Apparatuses and Methods for Adding Offset Delays to Signal Lines of Multi-Level Communication Architectures
Application:
15/994,862 →
Methods of Verifying Data Path Integrity
Application:
15/994,175 →
Data Erase Operations for a Memory System
Application:
15/994,151 →
Methods of Operating a Memory with Redistribution of Received Data
Application:
15/993,968 →
Sensing Operations in Memory by Comparing Inputs in a Sense Amplifier
Application:
15/994,307 →
Apparatuses Containing FinFETS
Application:
15/995,047 →
Logical-To-Physical Data Structures for Tracking Logical Block Addresses Indicative of a Collision
Application:
15/994,669 →
Wear Leveling
Application:
15/992,972 →
Transmission of Vehicle Route Information by Passive Devices
Application:
15/993,119 →
Read Look Ahead Data Size Determination
Application:
15/993,007 →
Methods of Forming an Array of Elevationally-Extending Strings of Memory Cells Having a Stack Comprising Vertically-Alternating Insulative Tiers and Wordline Tiers and Horizontally-Elongated Trenches in the Stack
Application:
15/992,959 →
Segmented Digital Die Ring
Application:
15/993,364 →
Pitch Reduction Technology Using Alternating Spacer Depositions During the Formation of a Semiconductor Device and Systems Including Same
Application:
15/993,568 →
Performing an Operation on a Memory Cell of a Memory System at a Frequency Based on Temperature
Application:
15/991,822 →
Determining Validity of Data Read from Memory by a Controller
Application:
15/991,463 →
Power Management Integrated Circuit with Embedded Address Resolution Protocol Circuitry
Application:
15/990,497 →
Apparatuses and Methods for Pin Capacitance Reduction Including Bond Pads and Circuits in a Semiconductor Device
Application:
15/990,370 →
Methods and Systems for Parsing and Executing Instructions to Retrieve Data Using Autonomous Memory
Application:
15/989,920 →
Progressive Length Error Control Code
Application:
15/988,962 →
Progressive Length Error Control Code
Application:
15/988,968 →
Feram-Dram Hybrid Memory
Application:
15/987,435 →
Memory Arrays and Methods of Forming an Array of Memory Cells
Application:
15/987,613 →
Semiconductor Layered Device with Data Bus Inversion
Application:
15/987,895 →
Memory Cell State in a Valley Between Adjacent Data States
Application:
15/987,414 →
Memory Devices Having Source Lines Directly Coupled to Body Regions and Methods
Application:
15/985,973 →
Semiconductor Devices Including Two-Dimensional Material Structures
Application:
15/986,129 →
Semiconductor Memory Device Having Plural Chips Connected by Hybrid Bonding Method
Application:
15/986,697 →