Semiconductor memory device having plural chips connected by hybrid bonding method

1. An apparatus comprising:

a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays; and

a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits,

wherein the first and second semiconductor chips are stacked with each other so that each of the plurality of first bonding electrodes is electrically connected to an associated one of the plurality of second bonding electrodes,

wherein each of the memory cell arrays includes a plurality of first signal lines extending in a first direction, a plurality of second signal lines extending in a second direction different from the first direction, and a plurality of memory cells each disposed on an associated one of intersections of the plurality of first and plurality of second signal lines,

wherein the plurality of memory cell arrays include first and second memory cell arrays adjacent in the second direction to each other,

wherein the plurality of first bonding electrodes include:

a first group located at one end of the first memory cell array in the first direction and electrically connected to predetermined ones of the plurality of first signal lines in the first memory cell array;

a second group located at another end of the first memory cell array in the first direction and electrically connected to remaining ones of the plurality of first signal lines in the first memory cell array; and

a third group located at one end of the second memory cell array in the first direction and electrically connected to predetermined ones of the plurality of first signal lines in the second memory cell array, a position of the third group in the first direction being located between positions of the first and second groups in the first direction.

2. The apparatus of claim 1 , wherein the plurality of first bonding electrodes further include a fourth group located at another end of the second memory cell array in the first direction and electrically connected to remaining ones of the plurality of first signal lines in the second memory cell array, the position of the second group in the first direction being located between positions of the third and fourth groups in the first direction.

3. The apparatus of claim 2 , wherein the plurality of first bonding electrodes further include a fifth group located at one end of the first memory cell array in the second direction and electrically connected to predetermined ones of the plurality of second signal lines in the first memory cell array, a position of the fifth group in the first direction overlapping with a position of the third group in the first direction.

4. The apparatus of claim 3 , wherein the plurality of first bonding electrodes further include a sixth group located at one end of the second memory cell array in the second direction and electrically connected to predetermined ones of the plurality of second signal lines in the second memory cell array, a position of the sixth group in the first direction overlapping with the position of the second group in the first direction.

5. The apparatus of claim 4 , wherein the plurality of second bonding electrodes include seventh, eighth, ninth, tenth, eleventh, and twelfth groups electrically connected to the first, second, third, fourth, fifth, and sixth groups, respectively.

6. The apparatus of claim 5 , wherein the second semiconductor chip further includes:

a first wiring layer having a plurality of first wirings extending in the first direction, one of the plurality of first wirings overlapping with the plurality of second bonding electrodes; and

a second wiring layer having a plurality of second wirings extending in the second direction, one of the plurality of second wirings overlapping with the plurality of second bonding electrodes.

7. The apparatus of claim 6 , wherein another one of the plurality of second wirings extends between the seventh and ninth groups so as not to overlap with the plurality of second bonding electrodes.

8. The apparatus of claim 7 , wherein the second semiconductor chip further includes a third wiring layer having a third wiring extending in the first and second directions so as not to overlap with the plurality of second bonding electrodes.

9. An apparatus comprising:

a plurality of memory cell arrays each including a plurality of first signal lines extending in a first direction, a plurality of second signal lines extending in a second direction different from the first direction, and a plurality of memory cells each disposed on an associated one of intersections of the plurality of first and plurality of second signal lines; and

a plurality of first bonding electrodes each electrically connected to an associated one of the plurality of first signal lines,

wherein the plurality of memory cell arrays are arranged in a plurality of rows, each including memory cell arrays of the plurality of memory cell arrays arranged in the first direction, and the plurality of rows are arranged in the second direction, and

wherein positions of the memory cell arrays of the plurality of memory cell arrays in adjacent rows of the plurality of rows are shifted half pitch in the first direction.

10. The apparatus of claim 9 , wherein the plurality of first bonding electrodes are grouped in a plurality of first groups, each of the plurality of first groups are arranged along a boundary of adjacent memory cell arrays of the plurality of memory cell arrays in the first direction.

11. The apparatus of claim 10 , further comprising a plurality of second bonding electrodes each electrically connected to an associated one of the plurality of second signal lines.

12. The apparatus of claim 11 , wherein the plurality of second bonding electrodes are grouped in a plurality of second groups, each of the plurality of second groups are arranged along a boundary of adjacent memory cell arrays of the plurality of memory cell arrays in the second direction.

13. The apparatus of claim 12 , wherein the plurality of first groups and the plurality of second groups are adjacent to each other in the second direction.

14. The apparatus of claim 9 , wherein the plurality of first signal lines are a plurality of bit lines and the plurality of second signal lines are a plurality of sub-word lines.

15. The apparatus of claim 14 , wherein the plurality of memory cells are a plurality of DRAM cells.

16. An apparatus comprising:

a plurality of unit areas each including a first logic circuit and a second logic circuit;

a plurality of first bonding electrodes electrically connected to the first logic circuits and arranged so as to overlap with the first logic circuit; and

a plurality of second bonding electrodes electrically connected to the second logic circuits and arranged so as to overlap with the second logic circuit,

wherein the plurality of unit areas are arranged in a plurality of rows, each including unit areas of the plurality of unit areas arranged in the first direction, and the plurality of rows are arranged in the second direction, and

wherein positions of the unit areas of the plurality of unit areas in adjacent rows of the plurality of rows are shifted half pitch in the first direction.

17. The apparatus of claim 16 , wherein the first logic circuits include sense amplifiers and the second logic circuits include sub-word drivers.

18. The apparatus of claim 17 , further comprising a first wiring layer having a plurality of first wirings extending in the first direction and a second wiring layer having a plurality of second wirings extending in the second direction.

19. The apparatus of claim 18 , further comprising a third wiring layer having a third wiring extending in the first and second directions so as not to overlap with the plurality of first and plurality of second bonding electrodes.

20. The apparatus of claim 19 , wherein the third wirings convey a predetermined signal asynchronous with an operation of the sense amplifiers and the sub-word drivers.