Patent Assignment
Reel/Frame 047282/0463
Supplement No. 9 to Patent Security Agreement
Recorded: 2018-08-09
Pages: 40
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2018-07-31
Assignee
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
1300 THAMES STREET, 4TH FLOOR, BALTIMORE, MARYLAND, 21231
Covered Properties
(545)
Utilizing Special Purpose Elements to Implement a Fsm
Interposer and Semiconductor Package
Patent:
9,922,924 →
Application:
15/369,834 →
Methods and Apparatuses Including a String of Memory Cells Having a First Select Transistor Coupled to a Second Select Transistor
Method and Structure Providing Optical Isolation of a Waveguide on a Silicon-on-Insulator Substrate
Microfeature Workpieces and Methods for Forming Interconnects in Microfeature Workpieces
Application:
15/662,204 →
Publication:
US 2017/0323828
Methods of Forming One or More Covered Voids in a Semiconductor Substrate
Solid State Storage Device with Quick Boot from Nand Media
Vertical Light Emitting Devices with Nickel Silicide Bonding and Methods of Manufacturing
Methods and Apparatus for Pattern Matching Using Redundant Memory Elements
Variable Resistance Memory Stack with Treated Sidewalls
Output Driver for Multi-Level Signaling
Method to Vertically Align Multi-Level Cells
Multi-Bias Level Generation and Interpolation
Analog Multiplexing Scheme for Decision Feedback Equalizers
Patent:
10,153,922 →
Application:
15/872,140 →
Internal Write Adjust for a Memory Device
Semiconductor Device with an Electrically-Coupled Protection Mechanism and Associated Systems, Devices, and Methods
Semiconductor Device with a Layered Protection Mechanism and Associated Systems, Devices, and Methods
System and Method for Controlling User Access to an Electronic Device
System and Method for Controlling User Access to an Electronic Device
Command Processing for a Storage System
Certifying Authenticity of Stored Code and Code Updates
In-Vehicle Monitoring and Reporting Apparatus for Vehicles
Data Strobe Gating
Patent:
10,176,862 →
Application:
15/880,994 →
Apparatuses and Methods for Providing Driving Signals in Semiconductor Devices
Apparatuses and Methods for Detecting a Row Hammer Attack with a Bandpass Filter
Forming Array Contacts in Semiconductor Memories
Identifying Suspicious Entities Using Autonomous Vehicles
Methods and Apparatuses for Dynamic Step Size for Impedance Calibration of a Semiconductor Device
Patent:
10,205,451 →
Application:
15/882,723 →
Semiconductor with Through-Substrate Interconnect
Apparatuses and Methods for Accessing Ferroelectric Memory Including Providing Reference Voltage Level
Volatile Memory Architecutre in Non-Volatile Memory Devices and Related Controllers
Application:
15/883,273 →
Publication:
US 2018/0158527
Write Level Initialization Synchronization
Logical Operations Using Memory Cells
Determination of a Match Between Data Values Stored by Several Arrays
Determination of a Match Between Data Values Stored by Three or More Arrays
Programmable Channel Equalization for Multi-Level Signaling
Channel Equalization for Multi-Level Signaling
Integrated Structures with Conductive Regions Having At Least One Element from Group 2 of the Periodic Table
Memory Network Methods, Apparatus, and Systems
Apparatuses and Methods for Controlling Refresh Operations
Transistors Comprising a Pair of Source/Drain Regions Having a Channel There-Between
Self Interference Noise Cancellation to Support Multiple Frequency Bands
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells
Patent:
10,236,301 →
Application:
15/890,503 →
A Programmable Charge-Storage Transistor, an Array of Elevationally-Extending Strings of Memory Cells, and a Method of Forming an Array of Elevationally-Extending Strings of Memory Cells
Techniques for Command Synchronization in a Memory Device
Semiconductor Assemblies Using Edge Stacking and Methods of Manufacturing the Same
Dqs Gating in a Parallelizer of a Memory Device
Memory Device Parallelizer
Writing Same Data on a Storage System
Self-Referencing Sensing Schemes with Coupling Capacitance
Methods of Forming Integrated Circuit Well Structures
Methods of Forming Circuit-Protection Devices
Repurposing Autonomous Vehicles for Package Delivery
Uniformity Between Levels of a Multi-Level Signal
Tapered Cell Profile and Fabrication
Tapered Memory Cell Profiles
Memory Cells with Asymmetrical Electrode Interfaces
Dopant-Modulated Etching for Memory Devices
Data Storage Device Idle Time Processing
Data Stream Identification and Processing in Data Storage Device
Input Buffer Circuit
Semiconductor Devices Comprising Nitrogen-Doped Gate Dielectric, and Methods of Forming Semiconductor Devices
Apparatuses, Circuits, and Methods for Biasing Signal Lines
Enabling Fast Pulse Operation
Apparatuses and Methods for Semiconductor Circuit Layout
Method and Apparatus Providing Pixel Array Having Automatic Light Control Pixels and Image Capture Pixels
Elevated Pocket Pixels, Imaging Devices and Systems Including the Same and Method of Forming the Same
Over-The-Air (Ota) Update for Firmware of a Vehicle Component
Unaligned Data Coalescing
Method for Substrate Moisture NCF Voiding Elimination
Methods and Apparatuses for Reflowing Conductive Elements of Semiconductor Devices
Recessed Access Devices And DRAM Constructions
End of Service Life of Data Storage Devices
Multiplication Operations in Memory
Modified Decode for Corner Turn
Apparatuses Having Memory Strings Compared to One Another Through a Sense Amplifier
Patent:
10,347,322 →
Application:
15/900,403 →
Performing an Additional Decoding Operation on an Identified Set of Bits of a Data Block
Performing a Decoding Operation to Simulate Switching a Bit of an Identified Set of Bits of a Data Block
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge-Storage Transistor
Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array
Apparatuses and Methods for Duty Cycle Distortion Correction of Clocks
Patent:
10,249,354 →
Application:
15/903,934 →
Doped Titanium Nitride Materials for Dram Capacitors, and Related Semiconductor Devices, Systems, and Methods
Generating Parity Data Based on a Characteristic of a Stream of Data
Apparatuses Comprising Protective Material Along Surfaces of Tungsten-Containing Structures
Using Sacrificial Polymer Materials in Semiconductor Processing
Dynamic Allocation of Resources of a Storage System Utilizing Single Root Input/Output Virtualization
Multiple Memory Type Memory Module Systems and Methods
Memory Module Data Object Processing Systems and Methods
Latency-Based Scheduling of Command Processing in Data Storage Devices
Meta Data Processing During Startup of Storage Devices
Storage Class Memory Status
Electronic Device with a Package-Level Thermal Regulator Mechanism and Associated Systems, Devices, and Methods
Electronic Device with a Card-Level Thermal Regulator Mechanism and Associated Systems, Devices, and Methods
Wiring with External Terminal
Oscillator Controlled Random Sampling Method and Circuit
Solid State Transducer Dies Having Reflective Features Over Contacts and Associated Systems and Methods
Signed Division in Memory
Storing Page Write Attributes
Adjusting a Parameter for a Programming Operation Based on the Temperature of a Memory System
Providing Data of a Memory System Based on an Adjustable Error Rate
Dynamic Error Handling in a Memory System
Systems and Methods for Improved Continuous Time Linear Equalization (Ctle)
Semiconductor Assemblies Having Semiconductor Material Regions with Contoured Upper Surfaces
Patent:
10,374,033 →
Application:
15/915,158 →
Non-Contact Electron Beam Probing Techniques and Related Structures
Apparatus and Method for Controlling Erasing Data in Ferroelectric Memory Cells
Patent:
10,229,727 →
Application:
15/919,994 →
Systems and Methods for Evaluating and Sharing Human Driving Style Information with Proximate Vehicles
Systems and Methods for Evaluating and Sharing Autonomous Vehicle Driving Style Information with Proximate Vehicles
Configuration of a Vehicle Based on Collected User Data
Word Line Cache Mode
Patent:
10,366,733 →
Application:
15/922,290 →
Stack Management in Memory Systems
Memory Device with an Array Timer Mechanism
Patent:
10,373,670 →
Application:
15/923,235 →
Canceling Memory Cell Variations by Isolating Digit Lines
Patent:
10,388,353 →
Application:
15/923,700 →
Black Box Data Recorder for Autonomous Driving Vehicle
Apparatuses and Methods for Adjusting a Phase Mixer Circuit
Interface for Memory Having a Cache and Multiple Independent Arrays
Tracking Data Temperatures of Logical Block Addresses
Patent:
10,365,854 →
Application:
15/924,951 →
Self-Selecting Memory Array with Horizontal Bit Lines
Boosted High-Speed Level Shifter
Patent:
10,396,795 →
Application:
15/926,548 →
Hierarchical Buffering Scheme to Normalize Non-Volatile Media Raw Bit Error Rate Transients
Converged Structure Supporting Buffering of Recent Writes and Overwrite Disturb Remediation
Patent:
10,381,073 →
Application:
15/926,986 →
Latency-Based Storage in a Hybrid Memory System
Latency-Based Storage in a Hybrid Memory System
Latency-Based Storage in a Hybrid Memory System
Sub-Threshold Voltage Leakage Current Tracking
Arrays Of Memory Cells Individually Comprising A Capacitor And A Transistor And Methods Of Forming Such Arrays
Patent:
10,229,874 →
Application:
15/928,956 →
Memory Block Select Circuitry Including Voltage Bootstrapping Control
Apparatuses and Methods for Storing and Writing Multiple Parameter Codes for Memory Operating Parameters
Methods for Detecting and Mitigating Memory Media Degradation and Memory Devices Employing the Same
Memory with Non-Volatile Configurations for Efficient Power Management and Operation of the Same
Specifying Media Type in Write Commands
Apparatuses and Methods for Providing Clock Signals in a Semiconductor Device
Patent:
10,339,998 →
Application:
15/937,552 →
Memory Tile Access and Selection Patterns
Methods and Apparatuses for Aligning Read Data in a Stacked Semiconductor Device
Apparatuses and Methods for Coupling Data Lines in Memory Devices
Application:
15/938,965 →
Publication:
US 2019/0304516
Memory Management
Apparatuses Including Buried Digit Lines
Resource Allocation in Memory Systems based on Operation Modes
Grouping Requests to Reduce Inter-Process Communication in Memory Systems
Optimization of Memory Systems based on Performance Goals
Memory Device Loopback Systems and Methods
Apparatuses and Methods for Coupling Contact Pads to a Circuit in a Semiconductor Device
Determination of Workload Distribution across Processors in a Memory System
Methods and Apparatuses for Self-Trimming of a Semiconductor Device
Memory Device and Method Having on-Board Processing Logic for Facilitating Interface with Multiple Processors, and Computer System Using Same
Meta Data Protection against Unexpected Power Loss in a Memory System
Apparatuses and Methods for Input Signal Receiver Circuits
Patent:
10,311,941 →
Application:
15/950,041 →
Area Efficient Implementation of a Product Code Error Correcting Code Decoder
High Throughput Bit Correction of Data Inside a Word Buffer for a Product Code Decoder
Determining Autonomous Vehicle Status Based on Mapping of Crowdsourced Object Data
Command Selection Policy with Read Priority
Address Map Caching for a Memory System
Defective Memory Unit Screening in a Memory System
Data Encoding Using Spare Channels
Apparatus, Systems, and Methods to Operate a Memory
Molding Compound Including a Carbon Nano-Tube Dispersion
Timing Circuit for Command Path in a Memory Device
Apparatuses and Methods for Duty Cycle Adjustment
Permutation Coding for Improved Memory Cell Operations
Apparatuses and Methods for Sensing Memory Cells
Patent:
10,424,372 →
Application:
15/957,173 →
Integrated Assemblies, and Methods of Forming Integrated Assemblies
Patent:
10,347,639 →
Application:
15/957,589 →
METHODS OF FORMING Si3NX, METHODS OF FORMING INSULATOR MATERIAL BETWEEN A CONTROL GATE AND CHARGE-STORAGE MATERIAL OF A PROGRAMMABLE CHARGE-STORAGE TRANSISTOR, AND METHODS OF FORMING AN ARRAY OF ELEVATIONALLY-EXTENDING STRINGS OF MEMORY CELLS AND A PROGRAMMABLE CHARGE-STORAGE TRANSISTOR MANUFACTURED IN ACCORDANCE WITH METHODS
Systems and Methods for Automatically Warning nearby Vehicles of Potential Hazards
Multi-Stage Memory Sensing
Sense Amplifier with Lower Offset and Increased Speed
Transaction Metadata
Error Correction Using Hierarchical Decoders
Apparatuses and Methods for Implementing Access Line Loads for Sense Amplifiers for Open Access Line Sensing
Apparatuses and Methods for Counter Update Operations
Access Schemes for Protecting Stored Data in a Memory Device
Non-Volatile Memory Devices and Systems with Volatile Memory Features and Methods for Operating the Same
Non-Volatile Memory Devices and Systems with Read-Only Memory Features and Methods for Operating the Same
Error Code Calculation on Sensing Circuitry
Stacked Semiconductor Die Assemblies with Die Support Members and Associated Systems and Methods
Apparatuses and Methods to Reverse Data Stored in Memory
Solid State Lighting Devices with Accessible Electrodes and Methods of Manufacturing
Cross-Point Memory Array and Related Fabrication Techniques
Cross-Point Memory Array and Related Fabrication Techniques
Buried Lines and Related Fabrication Techniques
Testing Semiconductor Devices Based on Warpage and Associated Methods
Managing a Memory System Including Memory Devices with Different Characteristics
Apparatuses and Methods for Refreshing Memory Cells of a Semiconductor Device
Sensing a Memory Cell
Sensing a Memory Cell
Allocating Variable Media Types of Memory Devices in a Memory System
Apparatuses and Methods for Asymmetric Input/Output Interface for a Memory
Tri-Level Dram Sense Amplifer
Stacked Memory Devices, Systems, and Methods
Apparatuses and Methods for Controlling Charge Pump Circuits
Methods for Reading Data from a Storage Buffer Including Delaying Activation of a Column Select
Transistors, Arrays of Transistors, Arrays of Memory Cells Individually Comprising a Capacitor and an Elevationally-Extending Transistor, and Methods of Forming an Array of Transistors
Patent:
10,388,658 →
Application:
15/965,632 →
Pre-Delay on-Die Termination Shifting
Patent:
10,367,512 →
Application:
15/965,663 →
Data Randomization for Flash Memory
Memory Arrays
Integrated Memory and Integrated Assemblies
Patent:
10,312,241 →
Application:
15/965,717 →
Secure Distribution of Secret Key Using a Monotonic Counter
Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry
Semiconductor Devices, and Related Memory Devices and Electronic Systems
Patent:
10,586,795 →
Application:
15/966,197 →
Methods of Forming Microelectronic Structures Having a Patterned Surface Structure
Autonomous Duty Cycle Calibration
Electronic Device with a Fuse Array Mechanism
Patent:
10,373,698 →
Application:
15/967,022 →
Bus Translator
Apparatuses and Methods for Semiconductor Circuit Layout
Memory Start Voltage Management
Methods Of Forming NAND Cell Units And NAND Cell Units
Apparatuses and Methods for Dynamic Voltage and Frequency Switching for Dynamic Random Access Memory
Plate Node Configurations and Operations for a Memory Array
Carrier Removal By Use of Multilayer Foil
Patent:
10,431,519 →
Application:
15/969,978 →
Determining Whether a Vehicle Should Be Configured for a Different Region
Reducing Supply Noise in Current Mode Logic Transmitters
Patent:
10,256,998 →
Application:
15/970,630 →
Key Generation and Secure Storage in a Noisy Environment
Integrated Assemblies Which Include Carbon-Doped Oxide, and Methods of Forming Integrated Assemblies
Patent:
10,381,352 →
Application:
15/971,210 →
Methods of Forming and Using Materials Containing Silicon and Nitrogen
Access Line Management for an Array of Memory Cells
Apparatuses and Methods to Perform Continuous Read Operations
Apparatuses and Methods for Accessing Variable Resistance Memory Device
Apparatus Having Memory Arrays and Having Trim Registers Associated with Memory Array Access Operation Commands
Apparatuses and Methods for Storing a Data Value in a Sensing Circuitry Element
Wiring with External Terminal
Apparatuses and Methods for Chip Identification in a Memory Package
Timing Control for Input Receiver
Memory Arrays
Memory Arrays
Integrated Circuits Having Parallel Conductors and Their Formation
Half-Width, Double Pumped Data Path
Patent:
10,388,362 →
Application:
15/974,120 →
Integrated Assemblies Having Ferroelectric Transistors with Body Regions Coupled to Carrier Reservoirs
Memory with Internal Refresh Rate Control
Electrically Conductive Laminate Structures
Memory Devices Having a Reduced Global Data Path Footprint and Associated Systems and Methods
Application:
15/975,556 →
Publication:
US 2019/0347219
Memory Devices Which Include Memory Arrays
Memory Buffer Management and Bypass
Prefetch Management for Memory
Prefetch Signaling in Memory System or Sub-System
Indication in Memory System or Sub-System of Latency Associated with Performing an Access Command
Cell Voltage Accumulation Discharge
Ferroelectric Memory Plate Power Reduction
Devices, Systems, and Methods of Reducing Chip Select
Methods for Parity Error Synchronization and Memory Devices and Systems Employing the Same
Methods for Parity Error Alert Timing Interlock and Memory Devices and Systems Employing the Same
Memory Device with an Input Signal Management Mechanism
Memory Device with a Latching Mechanism
Patent:
10,395,701 →
Application:
15/975,716 →
Arrays of Elevationally-Extending Strings of Memory Cells and Methods of Forming Memory Arrays
Memory Cells and Integrated Structures
Integrated Circuitry And 3D Memory
Methods for Fabricating 3D Semiconductor Device Packages, Resulting Packages and Systems Incorporating Such Packages
Patent:
10,319,696 →
Application:
15/976,398 →
Finer Grain Dynamic Random Access Memory
Tools and Systems for Processing One or More Semiconductor Devices, and Related Methods
Semiconductor Devices Having Electrostatic Discharge Layouts for Reduced Capacitance
Reduced Shifter Memory System
Patent:
10,354,717 →
Application:
15/976,698 →
Systems and Methods for Reducing Coupling Noise Between Propagation Lines for Die Size Efficiency
Patent:
10,403,353 →
Application:
15/976,705 →
Memory with a Reduced Array Data Bus Footprint
Patent:
10,366,743 →
Application:
15/976,716 →
Assemblies Having Conductive Structures Along Pillars of Semiconductor Material
Semiconductor Device with Pseudo Flow Through Scheme for Power Savings
Semiconductor Device with a Time Multiplexing Mechanism for Size Efficiency
Memory Device with a Signaling Mechanism
Patent:
10,373,654 →
Application:
15/976,737 →
Low Power Method and System for Signal Slew Rate Control
Light-Emitting Metal-Oxide-Semiconductor Devices and Associated Systems, Devices, and Methods
Solid State Transducer Devices, Including Devices Having Integrated Electrostatic Discharge Protection, and Associated Systems and Methods
Memory Device with a Clocking Mechanism
Patent:
10,395,702 →
Application:
15/977,125 →
Methods Used In Forming Integrated Circuitry Including Forming First, Second, and Third Contact Openings
Heat Spreaders for Use with Semiconductor Devices
Patent:
10,410,950 →
Application:
15/977,760 →
Variable Modulation Scheme for Memory Device Access or Operation
Multiplexing Distinct Signals on a Single Pin of a Memory Device
Multiple Concurrent Modulation Schemes in a Memory System
Communicating Data with Stacked Memory Dies
Memory System That Supports Dual-Mode Modulation
Test Mode Signal Distribution Schemes for Memory Systems and Associated Methods
Application:
15/977,959 →
Publication:
US 2019/0348138
Shifting Data in Sensing Circuitry
Apparatuses and Methods for Data Movement
Semiconductor Dice Assemblies, Packages and Systems, and Methods of Operation
Apparatus Having Dice to Perorm Refresh Operations
Power Reduction for a Sensing Operation of a Memory Cell
Channel-Scope Proximity Disturb and Defect Remapping Scheme for Non-Volatile Memory
Die-Scope Proximity Disturb and Defect Remapping Scheme for Non-Volatile Memory
Memory Die Remapping
Managing Data Disturbance in a Memory with Asymmetric Disturbance Effects
Forward and Reverse Translation for Dynamic Storage Media Remapping
Enhancing Nucleation in Phase-Change Memory Cells
Floating Gate Memory Cells in Vertical Memory
Integrated Assemblies and Methods of Forming Integrated Assemblies
Patent:
10,354,989 →
Application:
15/980,908 →
Integrated Circuit Structures And Methods Of Forming An Opening In A Material
Substrates, Structures Within A Scribe-Line Area Of A Substrate, And Methods Of Forming A Conductive Line Of A Redistribution Layer Of A Substrate And Of Forming A Structure Within A Scribe-Line Area Of The Substrate
Frame Protocol of Memory Device
Reconfigurable Memory Architectures
Memory System with a Variable Sampling Rate Mechanism
Application:
15/981,790 →
Publication:
US 2019/0354312
Memory System with Dynamic Calibration Using a Variable Adjustment Mechanism
Memory System with Dynamic Calibration Using a Trim Management Mechanism
Memory System Quality Integral Analysis and Configuration
Memory System Quality Margin Analysis and Configuration
Memory System Quality Threshold Intersection Analysis and Configuration
Semiconductor Devices Having Discretely Located Passivation Material, and Associated Systems and Methods
Memory Device Having Source Contacts Located at Intersections of Linear Portions of a Common Source, Electronic Systems, and Associated Methods
Solid State Lighting Devices Having Improved Color Uniformity and Associated Methods
Devices, Methods, and Systems Supporting on Unit Termination
Adaptive Scan Frequency for Detecting Errors in a Memory System
Methods of Forming a Semiconductor Structure and Methods of Forming Isolation Structures
Patent:
10,381,218 →
Application:
15/982,872 →
Probabilistic Event Detector for Fast Overwrite Disturb Remediation in Phase Change Media
Integrated Memory, Integrated Assemblies, and Methods of Forming Memory Arrays
Selection Component That Is Configured Based on an Architecture Associated with Memory Devices
Apparatuses and Methods for Fixing a Logic Level of an Internal Signal Line
Data Duplication in a Non-Volatile Memory
Time Indicator of Super Block Operations
Apparatuses and Methods for Sharing Transmission Vias for Memory Devices
Allocation of Overprovisioned Blocks for Minimizing Write Amplification in Solid State Drives
Enabling a Secure Boot from Non-Volatile Memory
Memory Devices Having Source Lines Directly Coupled to Body Regions and Methods
Semiconductor Devices Including Two-Dimensional Material Structures
Electronic Devices with Magnetic and Attractor Materials and Methods of Fabrication
Wireless Devices and Systems Including Examples of Compensating Power Amplifier Noise
Patent:
10,432,240 →
Application:
15/986,555 →
Apparatuses Comprising Memory Cells, and Apparatuses Comprising Memory Arrays
Semiconductor Memory Device Having Plural Chips Connected by Hybrid Bonding Method
Patent:
10,340,261 →
Application:
15/986,697 →
Memory Cell State in a Valley Between Adjacent Data States
Feram-Dram Hybrid Memory
Memory Arrays and Methods of Forming an Array of Memory Cells
Semiconductor Layered Device with Data Bus Inversion
Progressive Length Error Control Code
Patent:
10,409,680 →
Application:
15/988,962 →
Progressive Length Error Control Code
Methods and Systems for Parsing and Executing Instructions to Retrieve Data Using Autonomous Memory
Apparatuses and Methods for Pin Capacitance Reduction Including Bond Pads and Circuits in a Semiconductor Device
Application:
15/990,370 →
Publication:
US 2019/0363060
Power Management Integrated Circuit with Embedded Address Resolution Protocol Circuitry
Determining Validity of Data Read from Memory by a Controller
Performing an Operation on a Memory Cell of a Memory System at a Frequency Based on Temperature
Methods of Forming an Array of Elevationally-Extending Strings of Memory Cells Having a Stack Comprising Vertically-Alternating Insulative Tiers and Wordline Tiers and Horizontally-Elongated Trenches in the Stack
Patent:
10,388,665 →
Application:
15/992,959 →
Wear Leveling
Read Look Ahead Data Size Determination
Transmission of Vehicle Route Information by Passive Devices
Segmented Digital Die Ring
Pitch Reduction Technology Using Alternating Spacer Depositions During the Formation of a Semiconductor Device and Systems Including Same
Methods of Operating a Memory with Redistribution of Received Data
Data Erase Operations for a Memory System
Methods of Verifying Data Path Integrity
Sensing Operations in Memory by Comparing Inputs in a Sense Amplifier
Data Relocation in Memory Having Two Portions of Data
Logical-To-Physical Data Structures for Tracking Logical Block Addresses Indicative of a Collision
Apparatuses, Multi-Chip Modules and Capacitive Chips
Apparatuses and Methods for Adding Offset Delays to Signal Lines of Multi-Level Communication Architectures
Apparatuses Containing FinFETS
Application:
15/995,047 →
Publication:
US 2018/0294268
Integrated Circuitry, Memory Integrated Circuitry, And Methods Used In Forming Integrated Circuitry
Devices Including Memory Arrays, Row Decoder Circuitries and Column Decoder Circuitries
Semiconductor Constructions, and Semiconductor Processing Methods
Apparatuses and Methods for Random Number Generation
Using Counters to Efficiently Track Busy Time of Storage Systems
Dynamic Allocation of Volatile Memory to Storage Management Components of a Non-Volatile Storage Device
Event Logging in a Multi-Core System
Systems and Methods for a Centralized Command Address Input Buffer
Patent:
10,403,335 →
Application:
15/997,356 →
Simulating Access Lines
Device Having Multiple Channels with Calibration Circuit Shared by Multiple Channels
Methods of Forming Integrated Structures
Apparatuses and Methods for Adjusting Delay of Command Signal Path
Apparatuses and Methods for Providing Constant Current
Methods of Forming Magnetic Memory Cells and Semiconductor Devices
Forming Conductive Plugs for Memory Device
Memories Including Multiple Arrays of Non-Volatile Memory Cells Selectively Connected to Sense Circuitry Using Different Numbers of Data Lines
Methods and Apparatuses of Driver Circuits Without Voltage Level Shifters
Array Plate Short Repair
Weight Storage Using Memory Device
Fabrication of Electrodes for Memory Cells
Techniques for Programming Multi-Level Self-Selecting Memory Cell
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells, Methods Of Forming Polysilicon, Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor, And Electronic Components Comprising Polysilicon
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge Storage Transistor And Arrays Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge Storage Transistor
Integrated Circuitry
Image Processor Formed in an Array of Memory Cells
Patent:
10,440,341 →
Application:
16/002,644 →
Stacked Semiconductor Die Assemblies with High Efficiency Thermal Paths and Molded Underfill
Methods of Forming Integrated Assemblies Having Dielectric Regions Along Conductive Structures
Patent:
10,347,643 →
Application:
16/002,890 →
Memory as a Programmable Logic Device
Integrated Assemblies Comprising Stud-Type Capacitors
Methods of Forming a Self-Assembled Block Copolymer Material
Accessing Data in Memory
Encryption of Executables in Computational Memory
Processing in Memory (Pim) Capable Memory Device Having Timing Circuitry to Control Timing of Operations
Semiconductor Devices and Structures
Apparatuses and Methods for Memory Including Ferroelectric Memory Cells and Dielectric Memory Cells
Memory Devices Configured to Latch Data for Output in Response to an Edge of a Clock Signal Generated in Response to an Edge of Another Clock Signal
Memory Cells and Memory Arrays
Shifting Data
Magnetic Tunnel Junctions
Methods of Forming a Semiconductor Device Comprising First and Second Nitride Layers
Semiconductor Device Assemblies with Annular Interposers
Semiconductor Device Assemblies with Lids Including Circuit Elements
Sense Amplifier Constructions
Memory Cell And An Array Of Memory Cells
Transistors
Application:
16/007,139 →
Publication:
US 2018/0294194
Health Characteristics of a Memory Device
Methods of Sealing Openings, and Methods of Forming Integrated Assemblies
Patent:
10,290,534 →
Application:
16/007,361 →
Multi-Die Inductors with Coupled Through-Substrate via Cores
Generating and Using Invertible, Shortened Bose-Chaudhuri-Hocquenghem Codewords
3D Interconnect Multi-Die Inductors with Through-Substrate via Cores
Semiconductor Devices with Package-Level Configurability
Reduced Voltage Nonvolatile Flash Memory
Etched Trenches in Bond Materials for Die Singulation, and Associated Systems and Methods
Methods Of Forming An Array Comprising Pairs Of Vertically Opposed Capacitors And Arrays Comprising Pairs Of Vertically Opposed Capacitors
Apparatuses and Methods for Identifying Memory Devices of a Semiconductor Device Sharing an External Resistance
Memory Device with Dynamic Program-Verify Voltage Calibration
Semiconductor Device with a Multi-Layered Encapsulant and Associated Systems, Devices, and Methods
Electronic Device with a Reconfigurable Charging Mechanism
Color Filter Array, Imagers and Systems Having Same, and Methods of Fabrication and Use Thereof
Translation Lookaside Buffer in a Switch
Methods of Operating Memory
Apparatuses and Method for Reducing Sense Amplifier Leakage Current During Active Power-Down
Methods and Apparatuses Including a String of Memory Cells Having a First Select Transistor Coupled to a Second Select Transistor
Detecting Road Conditions Based on Braking Event Data Received from Vehicles
Memory Access Determination
Dynamic Memory Refresh Interval to Reduce Bandwidth Penalty
Downloading System Memory Data in Response to Event Detection
Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch Different from the First Pitch, and Methods of Forming Integrated Assemblies
Integrated Assemblies Having Bitline Contacts
Adaptive Watchdog in a Memory Device
Vehicle Navigation Using Object Data Received from Other Vehicles
Field Effect Transistor Constructions With Gate Insulator Having Local Regions Radially There-Through That Have Different Capacitance At Different Circumferential Locations Relative To A Channel Core Periphery
Apparatuses and Methods for Multiple Row Hammer Refresh Address Sequences
Shifter Circuits Having Registers Arranged in a Folded Topology
Managed Nand Cold Data Storage
Managed Nand Data Tagging
Managed Nand Data Compression
Memory Sub-System with Dynamic Calibration Using Component-Based Function(S)
Methods for Enhancing Adhesion of Three-Dimensional Structures to Substrates
Shared Error Detection and Correction Memory
Apparatuses and Method for Reducing Row Address to Column Address Delay
Differential Fuse-Readout Circuits for Electronic Devices
Patent:
10,304,554 →
Application:
16/013,668 →
Memory Devices Having Special Mode Access
Half-Frequency Command Path
Methods and Systems for Averaging Impedance Calibration
Individually Addressing Memory Devices Disconnected from a Data Bus
Write Signal Launch Circuitry for Memory Device
Patent:
10,418,090 →
Application:
16/014,539 →
Methods for on-Die Memory Termination and Memory Devices and Systems Employing the Same
Methods for Independent Memory Bank Maintenance and Memory Devices and Systems Employing the Same
Patent:
10,297,309 →
Application:
16/015,441 →
Method of Forming Photonics Structures
Memory Device with a Multiplexed Command/Address Bus
Data Recovery After Storage Failure in a Memory System
Managing Write Operations During a Power Loss
Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor
Wafer-Level Solid State Transducer Packaging Transducers Including Separators and Associated Systems and Methods
Adjustable Voltage Drop Detection Threshold in a Memory Device
Systems and Methods to Enable Identification of Different Data Sets
Backside Stealth Dicing Through Tape Followed by Front Side Laser Ablation Dicing Process
Apparatuses and Methods for Reducing Row Address to Column Address Delay for a Voltage Threshold Compensation Sense Amplifier
Semiconductor Devices and Systems Containing Nanofluidic Channels
Removing Polysilicon
Memory Cell Programming with a Programming Pulse Having a Plurality of Different Voltage Levels
Fuse-Array Element
Adaptive Communication Interface
Memory Devices and Systems with Parallel Impedance Adjustment Circuitry and Methods for Operating the Same
Apparatuses and Methods for Charge Pump Regulation
Memory Devices with Selective Page-Based Refresh
Programming of Memory Devices Responsive to a Stored Representation of a Programming Voltage Indicative of a Programming Efficiency
Methods and Apparatus for Pattern Matching Having Memory Cell Pairs Coupled in Series and Coupled in Parallel
Semiconductor Devices Having Through-Stack Interconnects for Facilitating Connectivity Testing
Systems and Apparatuses for a Configurable Temperature Dependent Reference Voltage Generator
Methods of Manufacturing Stacked Semiconductor Die Assemblies with High Efficiency Thermal Paths
Application:
16/020,567 →
Publication:
US 2018/0308785
Cold Fluid Semiconductor Device Release During Pick and Place Operations, and Associated Systems and Methods
Semiconductor Devices Including a Controller and Methods of Forming Such Devices
Vertical Ferroelectric Field Effect Transistor Constructions, Constructions Comprising A Pair Of Vertical Ferroelectric Field Effect Transistors, Vertical Strings Of Ferroelectric Field Effect Transistors, And Vertical Strings Of Laterally Opposing Pairs Of Vertical Ferroelectric Field Effect Transistors
Semiconductor Devices with Through Silicon Vias and Package-Level Configurability
Patent:
10,483,241 →
Application:
16/020,792 →
System and Method for Counting Fail Bit and Reading Out the Same
Variable Filter Capacitance
Semiconductor Device
Methods of Programming and Sensing in a Memory Device
Memory Devices Having Selectively Electrically Connected Data Lines
Semiconductor Packages and Devices
Stacked Memory Package Incorporating Millimeter Wave Antenna in Die Stack
Elevationally-Elongated Conductive Structure Of Integrated Circuitry, Method Of Forming An Array Of Capacitors, Method Of Forming DRAM Circuitry, And Method Of Forming An Elevationally-Elongated Conductive Structure Of Integrated Circuitry
Patent:
10,461,149 →
Application:
16/021,683 →
Method Of Forming An Array Of Capacitors, A Method Of Forming DRAM Circuitry, And A Method Of Forming An Elevationally-Elongated Conductive Structure Of Integrated Circuitry
Patent:
10,475,796 →
Application:
16/021,709 →
Memory Device and Method of Operation
Patent:
10,446,236 →
Application:
16/021,964 →
Monitoring and Charging Inhibit Bit-Line
Debugging a Semiconductor Device
Data Strobe Multiplexer
Data Strobe Calibration
Apparatuses and Methods for Switching Refresh State in a Memory Circuit
Ultrathin Solid State Dies and Methods of Manufacturing the Same
Apparatuses and Methods for Configurable Memory Array Bank Architectures
Patent:
10,372,330 →
Application:
16/022,421 →
Electronic Device with a Charging Mechanism
Patent:
10,211,725 →
Application:
16/022,444 →
Electronic Device with a Fuse Read Mechanism
Patent:
10,236,072 →
Application:
16/022,549 →
Resistive Memory Cell Structures and Methods
Program Progess Monitoring in a Memory Array
Programming Memories with Stepped Programming Pulses
Misplacement Mitigation Algorithm
Conductive Components and Memory Assemblies
Nand Temperature-Aware Operations
Host Timeout Avoidance in a Memory Device
Host Side Caching Security for Flash Memory
Secure Wireless Lock-Actuation Exchange
Host Accelerated Operations in Managed Nand Devices
Patent:
10,459,845 →
Application:
16/023,338 →
Managed Nand Power Management
Secure Logical-to-Physical Caching
Level Shifters, Memory Systems, and Level Shifting Methods
Multi-Function, Modular System for Network Security, Secure Communication, and Malware Protection
Managed Nand Performance Throttling
Multi-Level Cell Data Load Optimization
Application:
16/024,201 →
Publication:
US 2020/0004446
Temperature Sensitive Nand Programming
Patent:
10,446,237 →
Application:
16/024,316 →
Controlling Nand Operation Latency
Erasure of Multiple Blocks in Memory Devices
Shift Skip
Shifting Data in Sensing Circuitry
Systems and Methods for Forming Apertures in Microfeature Workpieces
Application:
16/025,332 →
Publication:
US 2018/0304411
Method, Apparatus, and System Providing an Imager with Pixels Having Extended Dynamic Range
Apparatus and Methods for Triggering Row Hammer Address Sampling
Method and Apparatus for Inductive Coupling Signal Transmission
Memory Device for a Hierarchical Memory Architecture
Method and Apparatus for a Volume Management System in a Non-Volatile Memory Device
Stack Refresh Control for Memory Device
Switched Interface Stacked-Die Memory Architecture
Systems and Methods for Double Data Rate Serialization in a Memory System
Package-On-Package Semiconductor Assemblies and Methods of Manufacturing the Same
Apparatuses and Methods for Providing Power for Memory Refresh Operations
Patent:
10,438,646 →
Application:
16/027,158 →
Methods of Operating a Memory Device
Semiconductor Devices and Methods of Fabrication
Apparatuses and Methods to Change Information Values
Recessed Transistors Containing Ferroelectric Material
Apparatus and Method for Instant-on Quadra-Phase Signal Generator
Shadow Cache for Securing Conditional Speculative Instruction Execution
Apparatuses and Methods for Controlling Wordlines and Sense Amplifiers
Separate Branch Target Buffers for Different Levels of Calls
Integrated Assemblies Having Thicker Semiconductor Material Along One Region of a Conductive Structure than Along Another Region
Patent:
10,446,577 →
Application:
16/029,144 →
Apparatus and Methods for Through Substrate via Test
Memory Cells Which Include Transistors Having GaP Channel Material
Application:
16/029,248 →
Methods for Generating Notifications for Updated Information from Mode Registers of a Memory Device to a Host and Memory Devices and Systems Employing the Same
Methods for Generating Notifications for Updated Information from Mode Registers of a Memory Device to a Host and Memory Devices and Systems Employing the Same
Storing Critical Data at a Memory System
Validation of a Symbol Response Memory
Interconnection for Memory Electrodes
Full Bias Sensing in a Memory Array
Error Correction Code Event Detection
Methods for Performing Multiple Memory Operations in Response to a Single Command and Memory Devices and Systems Employing the Same
Methods for Performing Multiple Memory Operations in Response to a Single Command and Memory Devices and Systems Employing the Same
Memory Arrays, and Methods of Forming Memory Arrays
Apparatuses and Methods for in-Memory Operations
Time-Based Access of a Memory Cell
Memory Cells and Memory Arrays
Determination of Data Integrity Based on Sentinel Cells
Apparatuses and Methods for Partitioned Parallel Data Movement
Memory Sub-System with Background Scan and Histogram Statistics
Enhanced Block Management for a Memory Sub-System
Memory Sub-System Codeword Quality Metrics Streaming
Methods and Apparatuses for Dynamic Step Size for Impedance Calibration of a Semiconductor Device
Wireless Devices and Systems Including Examples of Mixing Input Data with Coefficient Data
Secure Vehicular Communication
Secure Vehicular Services Communication
Array Data Bit Inversion
Memory Circuitry
Solid State Lighting Device with Different Illumination Parameters at Different Regions of an Emitter Array
Real Time Block Failure Analysis for a Memory Sub-System
Apparatuses and Methods Including Memory Commands for Semiconductor Memories
Apparatuses and Methods Including Memory Commands for Semiconductor Memories
Memory Devices and Apparatus Configured to Apply Positive Voltage Levels to Data Lines for Memory Cells Selected for and Inhibited from Programming
Apparatus and Methods Including Establishing a Negative Body Potential in a Memory Cell
Auto Injector with Temperature Control
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 7, 2016
From: SHIH, SHING-YIH
To: INOTERA MEMORIES, INC.
Reel/Frame 040845/0401 →
Change of Name
Oct 24, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY TAIWAN, INC.
Reel/Frame 044786/0244 →
Assignment of Assignor's Interest
Jan 16, 2018
From: BUTTERFIELD, JUSTIN D.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044626/0944 →
Assignment of Assignor's Interest
Jan 16, 2018
From: HOLLIS, TIMOTHY M.; LIN, FENG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044627/0050 →
Assignment of Assignor's Interest
Jan 19, 2018
From: PENNEY, DANIEL B.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045101/0916 →
Assignment of Assignor's Interest
Jan 22, 2018
From: SREERAMANENI, RAGHUKIRAN; TAYLOR, JENNIFER E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044689/0612 →
Assignment of Assignor's Interest
Jan 22, 2018
From: SREERAMANENI, RAGHUKIRAN; PENNEY, DANIEL B.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044689/0719 →
Assignment of Assignor's Interest
Jan 24, 2018
From: ZHOU, WEI; STREET, BRET K.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044715/0074 →
Assignment of Assignor's Interest
Jan 24, 2018
From: ZHOU, WEI; STREET, BRET K.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044714/0701 →
Assignment of Assignor's Interest
Jan 31, 2018
From: LIANG, QING; HE, DEPING
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044789/0461 →
Assignment of Assignor's Interest
Feb 1, 2018
From: MICRON TECHNOLOGY TAIWAN, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044802/0026 →
Assignment of Assignor's Interest
May 10, 2018
From: MICHAEL J. BERNHARDT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045774/0270 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →