Sensing operations in memory by comparing inputs in a sense amplifier

1. An apparatus, comprising:

an array of memory cells; and

a controller coupled to the array configured to:

sense a first memory cell based upon a first input associated with the first memory cell and a second input and a third input associated with a second memory cell, wherein a data state of the first memory cell is sensed by comparing the first input to an average of the second and third inputs in a first sense amplifier associated with the first memory cell.

2. The apparatus of claim 1 , wherein the second input corresponds to a first data state and the third input corresponds to a second data state and wherein the first and second data states are complementary.

3. The apparatus of claim 1 , wherein the first memory cell and the second memory cell are coupled to a first sense amp associated with the first memory cell.

4. The apparatus of claim 1 , wherein the second memory cell is coupled to a second sense amp associated with the second memory cell.

5. The apparatus of claim 1 , wherein the first memory cell and the second memory cell are coupled to an access line.

6. An apparatus, comprising:

an array of memory cells including a first memory cell coupled to a first sense amp, a second memory cell coupled to a second sense amp, and a third memory cell coupled to a third sense amp; and

a controller configured to:

sense the first memory cell by inputting a first signal associated with the first memory cell to the first sense amp and a second signal and a third signal associated with a fourth memory cell to the first sense amp, wherein an output of the first sense amp corresponding to a data state of the first memory cell is based a difference between the first signal and an average of the second and third signals.

7. The apparatus of claim 6 , wherein the first sense amp includes a first input configured to receive the first signal, a second input configured to receive the first signal, third input configured to receive the second signal, and a fourth input configured to receive the third signal.

8. The apparatus of claim 6 , wherein the second signal is a voltage that corresponds to first data state and third signal is a voltage that corresponds to a second data state.

9. The apparatus of claim 6 , wherein the controller is configured to sense the second memory cell by inputting a fourth signal associated with the second memory cell to the second sense amp and the second and third signals associated with the fourth memory cell to the second sense amp.

10. The apparatus of claim 6 , wherein the controller is configured to sense the third memory cell by inputting a fifth signal associated with the third memory cell to the third sense amp and the second and third signals associated with the fourth memory cell to the third sense amp.

11. A method, comprising:

inputting a signal associated with a memory cell and complementary signals associated with another memory cell to a sense amp;

sensing the memory cell at a first data state in response to the signal associated with the memory cell being greater than an average of the complementary signals; and

sensing the memory cell at a second data state in response to the signal associated with the memory cell being less than an average of the complementary signals.

12. The method of claim 11 , wherein sensing the memory cell at the first data state includes latching a signal in the sense amp that is greater than the average of the complementary signals.

13. The method of claim 11 , wherein sensing the memory cell at the first data state includes latching a signal in the sense amp that is less than the average of the complementary signals.

14. The method of claim 11 , further including programming the another memory cell with complementary signals that include a signal corresponding to the first data state and a signal corresponding to the second data state.

15. The method of claim 11 , further including inputting the complementary signals associated with the another memory cell as a first signal and a second signal to another sense amp associated with the another sense amp.

16. The method of claim 15 , further including sensing the another memory cell at a first data state in response to the first signal corresponding to the first data state and the second signal corresponding to the second data state.

17. The method of claim 16 , further including sensing the another memory cell at a second data state in response to the first signal corresponding to the second data state and the second signal corresponding to the second data state.

18. An apparatus, comprising:

an array of memory cells including a first memory cell coupled to a first sense amp, a second memory cell coupled to a second sense amp, and a third memory cell coupled to a third sense amp; and

a controller configured to:

sense the first memory cell by inputting a first signal associated with the first memory cell to the first sense amp and a second signal and a third signal associated with a fourth memory cell to the first sense amp; and

sense the second memory cell by inputting a fourth signal associated with the second memory cell to the second sense amp and the second and third signals associated with the fourth memory cell to the second sense amp.

19. An apparatus, comprising:

an array of memory cells including a first memory cell coupled to a first sense amp, a second memory cell coupled to a second sense amp, and a third memory cell coupled to a third sense amp; and

a controller configured to:

sense the first memory cell by inputting a first signal associated with the first memory cell to the first sense amp and a second signal and a third signal associated with a fourth memory cell to the first sense amp; and

sense the third memory cell by inputting a fourth signal associated with the third memory cell to the third sense amp and the second and third signals associated with the fourth memory cell to the third sense amp.