Multi-stage memory sensing

1. A method, comprising:

asserting a word line signal associated with a memory cell during a read operation of the memory cell;

coupling the memory cell with a digit line associated with the memory cell based at least in part on the asserting of the word line signal;

activating a transistor to couple, during the read operation, an amplifier capacitor with the digit line;

deactivating the transistor for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled with the digit line;

reactivating the transistor after the portion of the read operation to recouple the amplifier capacitor with the digit line; and

determining a value stored on the memory cell after reactivating the transistor.

2. The method of claim 1 , further comprising:

asserting the word line signal at the same time as or before deactivating the transistor for the portion of the read operation.

3. The method of claim 1 , further comprising:

comparing a voltage at a first node of the amplifier capacitor to a reference voltage, wherein determining the value is based at least in part on the comparison.

4. The method of claim 1 , further comprising:

identifying that a trigger condition is satisfied after reactivating the transistor; and

activating a latch coupled with the amplifier capacitor based at least in part on identifying that the trigger condition is satisfied.

5. The method of claim 4 , further comprising:

determining that a timer having a predetermined duration has expired after reactivating the transistor, wherein identifying that the trigger condition is satisfied is based at least in part on determining that the timer has expired.

6. The method of claim 1 , further comprising:

asserting a control signal coupled to a gate of the transistor, wherein activating the transistor is based at least in part on the asserting of the control signal; and

deasserting the control signal, wherein deactivating the transistor is based in part on the deasserting of the control signal.

7. The method of claim 1 , wherein the amplifier capacitor is coupled to a drain of the transistor and the digit line is coupled to a source of the transistor.

8. The method of claim 1 , wherein activating the transistor causes an electric charge to be transferred to the amplifier capacitor from the memory cell, and wherein determining the value is based at least in part on the transferred charge.

9. The method of claim 1 , further comprising:

pre-charging the amplifier capacitor to a predetermined charge before activating the transistor.

10. The method of claim 1 , wherein the transistor is part of a cascode.

11. A method, comprising:

coupling an amplifier capacitor with a second transistor by activating a first transistor, wherein the second transistor couples the first transistor with a digit line associated with a memory cell during a read operation of the memory cell;

coupling the memory cell with the digit line;

isolating the amplifier capacitor from the second transistor while the memory cell is coupled with the digit line by deactivating the first transistor for a portion of the read operation;

recoupling the amplifier capacitor with the second transistor by reactivating the first transistor after the portion of the read operation; and

determining a value stored on the memory cell after reactivating the first transistor.

12. The method of claim 11 , wherein the second transistor is activated for an entire duration of the read operation.

13. The method of claim 11 , wherein activating the first transistor causes electric charge to be transferred to the amplifier capacitor from the memory cell, and wherein determining the value is based at least in part on the transferred charge.

14. The method of claim 11 , further comprising:

comparing a voltage at a first node of the amplifier capacitor to a reference voltage, wherein determining the value is based at least in part on the comparison.

15. The method of claim 11 , further comprising:

identifying that a trigger condition is satisfied after reactivating the first transistor; and

activating a latch coupled with the amplifier capacitor based at least in part on identifying that the trigger condition is satisfied.

16. The method of claim 15 , further comprising:

determining that a timer having a predetermined duration has expired after reactivating the first transistor, wherein identifying that the trigger condition is satisfied is based at least in part on determining that the timer has expired.

17. The method of claim 11 , wherein:

a first node of the amplifier capacitor is coupled to a drain of the first transistor, and

a source of the first transistor is coupled to a drain of the second transistor.

18. An apparatus, comprising:

a ferroelectric memory cell coupled with a digit line;

an amplifier capacitor;

a first transistor coupled with the digit line and configured to be activated for a duration of a read operation on the ferroelectric memory cell; and

a second transistor coupled with the first transistor and the amplifier capacitor, the second transistor configured to:

activate for the read operation;

deactivate for a portion of the read operation; and

reactivate after the portion of the read operation, wherein the first transistor and the second transistor are configured to establish an electrical connection between the amplifier capacitor and the digit line when the second transistor is activated and reactivated during the read operation.

19. The apparatus of claim 18 , wherein:

a source of the first transistor is coupled with the digit line and a drain of the first transistor is coupled with a source of the second transistor, and

a drain of the second transistor is coupled with the amplifier capacitor.

20. The apparatus of claim 18 , further comprising:

a sense amplifier coupled with the amplifier capacitor and the second transistor, wherein the sense amplifier is configured to determine a value stored on the ferroelectric memory cell.

21. A memory device, comprising:

a memory cell;

a digit line coupled with the memory cell;

an amplifier capacitor coupled with the digit line;

a controller configured to:

assert, during a read operation of the memory cell, a word line signal associated with the memory cell;

couple the memory cell with the digit line based at least in part on the asserting of the word line signal;

activate a transistor to couple, during the read operation, the amplifier capacitor with the digit line;

deactivate the transistor for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled with the digit line;

reactivate the transistor after the portion of the read operation to recouple the amplifier capacitor with the digit line; and

determine a value stored on the memory cell after reactivating the transistor.

22. The memory device of claim 21 , wherein the controller is further configured to:

assert the word line signal associated with the memory cell at the same time as or before the controller deactivates the transistor for the portion of the read operation.

23. The memory device of claim 22 , wherein the controller is further configured to:

compare a voltage at a first node of the amplifier capacitor to a reference voltage, wherein determining the value is based at least in part on the comparison.

24. The memory device of claim 22 , wherein the controller is further configured to:

identify that a trigger condition is satisfied after reactivating the transistor; and

activate a latch coupled with the amplifier capacitor based at least in part on identifying that the trigger condition is satisfied.

25. The memory device of claim 24 , wherein the controller is further configured to:

determine that a timer having a predetermined duration has expired after reactivating the transistor, wherein identifying that the trigger condition is satisfied is based at least in part on determining that the timer has expired.