Integrated circuitry, memory integrated circuitry, and methods used in forming integrated circuitry

1. Integrated circuitry comprising:

a three-dimensional (3D) array comprising tiers of electronic components;

a circuit-operative stair-step structure;

an upper conductive landing adjacent and above the circuit-operative stair-step structure; and

the circuit-operative stair-step structure comprising a circuit-operative stair flight, the stair flight comprising:

vertically alternating insulative tiers and conductive tiers;

a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier; and

an uppermost of the plurality of stairs that is below the upper conductive landing having at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure.

2. The integrated circuitry of claim 1 comprising a circuit-inoperative stair-step structure opposite and facing the circuit-operative stair flight.

3. The integrated circuitry of claim 1 wherein the circuit-operative stair-step structure is one circuit-operative stair-step structure, the integrated circuitry comprising:

another circuit-operative stair-step structure adjacent and below the upper conductive landing; and wherein:

the one conductive tier that does not extend into the 3D array from the one circuit-operative stair-step structure does extend into the 3D array from the another circuit-operative stair-step structure;

the another circuit-operative stair-step structure comprising a stair comprising the one conductive tier that does extend into the 3D array from the another circuit-operative stair-step structure; and

the stair in the another circuit-operative stair-step structure being contacted by an elevationally-extending conductive via.

4. The integrated circuitry of claim 3 comprising a circuit-inoperative stair-step structure opposite and facing the another circuit-operative stair-step structure and which is between the another circuit-operative stair-step structure and the one circuit-operative stair-step structure.

5. The integrated circuitry of claim 1 wherein the electronic components comprise transistors.

6. The integrated circuitry of claim 1 wherein the electronic components comprise memory cells.

7. The integrated circuitry of claim 1 wherein the uppermost stair has at least two conductive tiers therein that do not extend into the 3D array.

8. The integrated circuitry of claim 7 wherein the uppermost stair has at least three conductive tiers therein that do not extend into the 3D array.

9. The integrated circuitry of claim 1 comprising a gap between the uppermost stair and the upper conductive landing.

10. The integrated circuitry of claim 1 wherein all of the stairs of the plurality of stairs individually comprise one of the conductive tiers atop and contacting an underlying one of the insulative tiers.

11. Integrated circuitry comprising:

a three-dimensional (3D) array comprising tiers of electronic components;

a circuit-operative stair-step structure;

an upper landing adjacent and above the circuit-operative stair-step structure;

the circuit-operative stair-step structure comprising:

vertically alternating insulative tiers and conductive tiers;

a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;

an uppermost of the plurality of stairs that is below the upper landing having at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure; and

wherein a stair that is immediately under the uppermost stair has at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure.

12. Integrated circuitry comprising:

a three-dimensional (3D) array comprising tiers of electronic components;

a circuit-operative stair-step structure;

an upper landing adjacent and above the circuit-operative stair-step structure;

the circuit-operative stair-step structure comprising:

vertically alternating insulative tiers and conductive tiers;

a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;

an uppermost of the plurality of stairs that is below the upper landing having at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure; and

wherein multiple of the stairs of the plurality of stairs that are successively immediately under the uppermost stair individually have at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure.

13. Integrated circuitry comprising:

a three-dimensional (3D) array comprising tiers of electronic components;

a circuit-operative stair-step structure;

an upper landing adjacent and above the circuit-operative stair-step structure; and

the circuit-operative stair-step structure comprising:

vertically alternating insulative tiers and conductive tiers;

a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;

an uppermost of the plurality of stairs that is below the upper landing having a dummy conductive tier therein; and

wherein a stair that is immediately under the uppermost stair has a dummy conductive tier therein.

14. Integrated circuitry comprising:

a three-dimensional (3D) array comprising tiers of electronic components;

a circuit-operative stair-step structure;

an upper landing adjacent and above the circuit-operative stair-step structure; and

the circuit-operative stair-step structure comprising:

vertically alternating insulative tiers and conductive tiers;

a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;

an uppermost of the plurality of stairs that is below the upper landing having a dummy conductive tier therein; and

wherein multiple of the stairs of the plurality of stairs that are successively immediately under the uppermost stair individually have a dummy conductive tier therein.

15. Memory integrated circuitry comprising:

an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor, the array comprising vertically alternating insulative tiers and wordline tiers;

a circuitry region adjacent the array and comprising a plurality of circuit-operative stair-step structures having an upper conductive landing between and above immediately adjacent of the circuit-operative stair-step structures of the plurality of circuit-operative stair-step structures, the circuit-operative stair-step structures individually comprising:

some of the vertically alternating insulative tiers and the wordline tiers;

a plurality of stairs individually comprising one of the wordline tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the wordline tiers and only one of the insulative tiers, the only one wordline tier of individual of the at least some of the stairs of the plurality of stairs extending into the array and being directly electrically coupled to at least one of the programmable charge-storage transistors in that one wordline tier; and

at least one of the circuit-operative stair-step structures of the plurality of circuit-operative stair-step structures having an uppermost of the plurality of stairs therein that is below the upper conductive landing that is between the at least one circuit-operative stair-step structure and the circuit-operative stair-step structure of the plurality of circuit-operative stair-step structures that is immediately adjacent the at least one circuit-operative stair-step structure towards the array, said uppermost stair having a dummy wordline tier therein.

16. The memory integrated circuitry of claim 15 wherein said uppermost stair comprises at least two dummy wordline tiers and at least two of the insulative tiers therein.

17. The memory integrated circuitry of claim 15 wherein the wordline tier that is the dummy wordline tier in the one circuit-operative stair-step structure is an active wordline tier in said immediately adjacent circuit-operative stair-step structure of the plurality of circuit-operative stair-step structures and a stair of the active wordline tier in said immediately adjacent circuit-operative stair-step structure being contacted by an elevationally-extending conductive via, the active wordline tier in said immediately adjacent circuit-operative stair-step structure extending into the array of elevationally-extending strings of memory cells from said immediately adjacent circuit-operative stair-step structure.

18. The memory integrated circuitry of claim 15 comprising NAND architecture.

19. Integrated circuitry comprising:

a three-dimensional (3D) array of electronic components;

a circuit-operative stair-step structure electrically coupled to the electronic components of the 3D array;

an upper landing adjacent and above the circuit-operative stair-step structure;

the circuit-operative stair-step structure comprising:

vertically alternating insulative tiers and conductive tiers;

a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers, at least some of the stairs of the plurality of stairs individually having only one of the conductive tiers and only one of the insulative tiers, the respective only ones of the conductive tiers extending into the array and directly electrically coupling with ones of the electronic components; and

an uppermost of the plurality of stairs that is below the upper landing comprising at least two of the conductive tiers and at least two of the insulative tiers;

a gap between the uppermost stair and the upper landing, the gap extending through another one of the conductive tiers that is not one of said respective only ones of the conductive tiers extending into the array; and

wherein the gap comprises at least one circuit-inoperative stair-step comprising said another one conductive tier of the conductive tiers that is not one of said respective only ones of the conductive tiers extending into the array.

20. A method used in forming integrated circuitry, comprising:

forming a stack of vertically alternating tiers of different composition materials;

forming a stair-step structure into the stack and forming an upper landing adjacent and above the stair-step structure, the stair-step structure being formed to comprise:

vertically alternating tiers of the different composition materials;

a plurality of stairs individually comprising two of the tiers of different composition materials, at least some of the stairs of the plurality of stairs individually having only two tiers that are each only of a different one of the different composition materials; and

an upper of the stairs of the plurality of stairs that is below the upper landing comprising at least four of the tiers of different composition materials;

wherein the stairs of the plurality of stairs individually comprise a rise and a run, and

further comprising:

at least partially translating the stair-step structure deeper into the stack by etching deeper into the stack; and

using the upper stair as masking material to preclude forming a gap between the run and the rise of an immediately adjacent of the stairs of the plurality of stairs that is below the upper stair during said etching.

21. The method of claim 20 wherein the upper stair is the uppermost stair of the stair-step structure.

22. The method of claim 21 comprising forming a gap between the uppermost stair and the upper landing.

23. The method of claim 22 comprising forming the gap to comprise at least one stair-step comprising two of the tiers of different composition materials.

24. The method of claim 22 comprising forming the gap to comprise opposing and facing stair-steps individually having at least one stair-step comprising two of the tiers of different composition materials.

25. Integrated circuitry comprising:

a three-dimensional (3D) array comprising tiers of electronic components;

a circuit-operative stair-step structure comprising a stadium comprising laterally-opposing stair flights in a vertical cross-section, one of the laterally-opposing stair flights being a circuit-operative stair flight inside the stadium, another of the laterally-opposing stair flights being a circuit-inoperative stair flight inside the stadium, laterally-opposing sides of the stadium comprising vertically alternating insulative tiers and conductive tiers;

each of the circuit-operative stair flight inside the stadium and the circuit-inoperative stair flight inside the stadium comprising a plurality of stairs individually comprising one of the conductive tiers and one of the insulative tiers;

at least some of the stairs of the plurality of stairs in the circuit-operative stair flight inside the stadium individually having only one of the conductive tiers and only one of the insulative tiers, the only one conductive tier extending into one of the tiers of the 3D array of the electronic components and being electrically coupled to at least one of the electronic components in that one tier;

an upper landing adjacent and above the circuit-operative stair flight, the upper landing comprising another one of the conductive tiers or another one of the insulative tiers and that is an uppermost tier of one of the laterally-opposing sides of the stadium; and

an uppermost of the plurality of stairs in the circuit-operative stair flight that is below the upper landing and that is inside the stadium having at least one conductive tier therein that does not extend into the 3D array of the electronic components from the circuit-operative stair-step structure.

26. The integrated circuitry of claim 25 wherein the another one is another one of the conductive tiers.

27. The integrated circuitry of claim 25 comprising multiple of said stadiums in said vertical cross-section.

28. The integrated circuitry of claim 27 wherein said multiple stadiums in said vertical cross-section individually have one of said upper landings that is coplanar with all said upper landings in the vertical cross-section.

29. The integrated circuitry of claim 28 wherein all said upper landings have their respective another one being another one of the conductive tiers.

30. The integrated circuitry of claim 25 comprising insulator material directly above the upper landing.

31. The integrated circuitry of claim 30 wherein the insulator material comprising silicon dioxide directly above the upper landing.

32. The integrated circuitry of claim 30 wherein the insulator material is directly against the upper landing.

33. The integrated circuitry of claim 25 comprising multiple of the insulative tiers and multiple of the conductive tiers above and between said uppermost of the plurality of stairs in the circuit-operative stair flight and said upper landing.

34. The integrated circuitry of claim 25 comprising memory circuitry, tiers of electronic components comprising an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor, the conductive tiers comprising wordline tiers.

35. The integrated circuitry of claim 34 comprising multiple of said stadiums in said vertical cross-section.

36. The integrated circuitry of claim 35 wherein said multiple stadiums in said vertical cross-section individually have one of said upper landings that is coplanar with all said upper landings in the vertical cross-section.

37. The integrated circuitry of claim 34 comprising insulator material directly above the upper landing.

38. The integrated circuitry of claim 37 wherein the insulator material comprising silicon dioxide directly above the upper landing.

39. The integrated circuitry of claim 37 wherein the insulator material is directly against the upper landing.

40. The integrated circuitry of claim 34 comprising multiple of the insulative tiers and multiple of the conductive tiers above and between said uppermost of the plurality of stairs in the circuit-operative stair flight and said upper landing.