Integrated assemblies having ferroelectric transistors with body regions coupled to carrier reservoirs
Some embodiments include an integrated assembly having a ferroelectric transistor body region between a first comparative digit line and a second comparative digit line. A carrier-reservoir structure is coupled with the ferroelectric transistor body region through an extension that passes along a side of the first comparative digit line. Some embodiments include an integrated assembly having a conductive structure over a carrier-reservoir structure. A bottom of the conductive structure is spaced from the carrier-reservoir structure by an insulative region. A ferroelectric transistor is over the conductive structure. The ferroelectric transistor has a bottom source/drain region over the conductive structure, has a body region over the bottom source/drain region, and has a top source/drain region over the body region. An extension extends upwardly from the carrier-reservoir structure, along a side of the conductive structure, and to a bottom of the body region. Some embodiments include methods of forming integrated assemblies.
1. An integrated assembly, comprising:
a ferroelectric transistor structure comprising a pillar extending vertically between a first comparative digit line and a second comparative digit line, the pillar having a first source/drain region directly against the first comparative digit line, a second source/drain region directly against the second comparative digit line and a ferroelectric transistor body region between the first and second source/drain regions; and
a carrier-reservoir structure coupled with the ferroelectric transistor body region through an extension that passes along a side of the first comparative digit line.
2. The integrated assembly of claim 1 comprising an insulative material between the side of the first comparative digit line and the extension.
3. The integrated assembly of claim 1 wherein;
the ferroelectric transistor body region comprises a first semiconductor material;
the carrier-reservoir structure comprises a second semiconductor material;
the extension comprises a third semiconductor material; and
the first, second and third semiconductor materials are a same composition as one another.
4. The integrated assembly of claim 3 wherein the first, second and third semiconductor materials consist essentially of silicon.
5. The integrated assembly of claim 1 wherein;
the ferroelectric transistor body region comprises a first semiconductor material;
the carrier-reservoir structure comprises a second semiconductor material;
the extension comprises a third semiconductor material; and
at least one of the first, second and third semiconductor materials is a different composition than at least one other of the first, second and third semiconductor materials.
6. The integrated assembly of claim 1 wherein the carrier-reservoir structure is a reservoir of holes.
7. The integrated assembly of claim 6 wherein the carrier-reservoir structure is coupled with a negative reference voltage source.
8. The integrated assembly of claim 1 wherein the carrier-reservoir structure is a reservoir of electrons.
9. The integrated assembly of claim 8 wherein the carrier-reservoir structure is coupled with a positive reference voltage source.
10. An integrated assembly, comprising:
a conductive structure over a carrier-reservoir structure; a bottom surface of the conductive structure being spaced from the carrier-reservoir structure by an insulative region;
a ferroelectric transistor over the conductive structure; the ferroelectric transistor having a pillar comprising a bottom source/drain region directly over and electrically coupled with the conductive structure, the pillar having a body region directly over the bottom source/drain region and a top source/drain region directly over the body region; and
an extension that extends upwardly from the carrier-reservoir structure, along a side of the conductive structure, and to a bottom of the body region; the extension being configured to provide carriers from the carrier-reservoir structure to the body region.
11. The integrated assembly of claim 10 wherein the insulative region is a first insulative region, and further comprising a second insulative region between the side of the conductive structure and the extension.
12. The integrated assembly of claim 11 wherein the first and second insulative regions are a same composition as one another.
13. The integrated assembly of claim 11 wherein the first and second insulative regions are different compositions relative to one another.
14. The integrated assembly of claim 10 wherein the top and bottom source/drain regions are n-type doped, and wherein the carrier-reservoir structure is p-type doped.
15. The integrated assembly of claim 10 wherein the top and bottom source/drain regions are p-type doped, and wherein the carrier-reservoir structure is n-type doped.
16. An integrated assembly, comprising:
a carrier-reservoir structure;
first comparative digit lines over the carrier-reservoir structure; the first comparative digit lines extending along a first direction;
ferroelectric transistor body regions over the first comparative digit lines;
lower source/drain, regions vertically between the body regions and the first comparative digit line;
extensions extending along the lower source/drain regions from the carrier-reservoir structure to the ferroelectric transistor body regions; the extensions being configured to provide carriers to the ferroelectric transistor body regions;
second comparative digit lines over the ferroelectric transistor body regions; the second comparative digit lines extending along the first direction;
wordlines adjacent the ferroelectric transistor body regions, and spaced from the ferroelectric transistor body regions by intervening regions comprising ferroelectric material; the wordlines extending along a second direction which crosses the first direction; and
the ferroelectric transistor body regions being comprised by memory cells of a memory array; each of the memory cells comprising one of the ferroelectric transistor body regions.
17. The integrated assembly of claim 16 wherein the carrier-reservoir structure is a reservoir of holes.
18. The integrated assembly of claim 16 wherein the carrier-reservoir structure is a reservoir of electrons.
19. The integrated assembly of claim 16 wherein the carrier-reservoir structure comprises silicon doped to a concentration of at least about 1×10 20 atoms/cm 3 with p-type dopant or n-type dopant.
20. The integrated assembly of claim 19 wherein the extensions comprise silicon doped to a concentration of at least about 1×10 17 atoms/cm 3 with said p-type dopant or n-type dopant.
21. The integrated assembly of claim 16 wherein the extensions are spaced from the first comparative digit lines by insulative material.
22. The integrated assembly of claim 16 wherein the memory cells are first memory cells of a first memory deck; and further comprising one or more additional memory decks stacked relative to the first memory deck in a multi-deck architecture.
23. The integrated assembly of claim 22 wherein the ferroelectric transistor body regions of the first memory deck are first ferroelectric transistor body regions; and wherein at least one of said one or more additional memory decks comprises second memory cells which include second ferroelectric transistor body regions.