IP Library Granted Patent US 10,381,218
Granted Patent B1
US 10,381,218 · App. 15/982,872 · Granted Aug 13, 2019

Methods of forming a semiconductor structure and methods of forming isolation structures

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Quick Facts
Patent No.
US 10,381,218
App. No.
15/982,872
Granted
Aug 13, 2019
Kind
B1
Abstract

A method of reducing silicon consumption of a silicon material. The method comprises cleaning a silicon material and subjecting the cleaned silicon material to a vacuum anneal at a temperature below a melting point of silicon and under vacuum conditions. The silicon material is subjected to additional process acts without substantially removing silicon of the silicon material. Additional methods of forming a semiconductor structure and forming isolation structures are also disclosed.

Claims (31)

1. A method of forming a semiconductor structure, comprising:

cleaning a silicon material at a chuck temperature between about 800° C. and about 1000° C.;

vacuum annealing the silicon material; and

forming an insulating material on the silicon material,

wherein the cleaning, the vacuum annealing, and the forming are conducted in a single processing apparatus.

2. The method of claim 1 , wherein cleaning a silicon material comprises cleaning an exposed surface of the silicon material.

3. The method of claim 1 , wherein cleaning a silicon material comprises removing contaminants comprising metals and polymers from the silicon material.

4. The method of claim 1 , wherein cleaning a silicon material comprises cleaning a silicon material consisting of silicon.

5. A method of forming a semiconductor structure, comprising:

cleaning a silicon material;

vacuum annealing the silicon material and further comprising exposing the silicon material to a silicon source gas during the vacuum annealing; and

forming an insulating material on the silicon material,

wherein the cleaning, the vacuum annealing, and the forming are conducted in a single processing apparatus.

6. The method of claim 1 , wherein cleaning a silicon material comprises removing silicon oxides from the silicon material.

7. The method of claim 1 , wherein vacuum annealing the silicon material comprises heating the silicon material to a chuck temperature between about 800° C. and about 1000° C. under a vacuum.

8. The method of claim 1 , wherein vacuum annealing the silicon material comprises conducting the vacuum anneal in situ in the single processing apparatus.

9. The method of claim 1 , wherein forming an insulating material on the silicon material comprises forming the insulating material in situ in the single processing apparatus.

10. The method of claim 1 , wherein the vacuum annealing and the forming are conducted in a single chamber of the single processing apparatus.

11. The method of claim 10 , further comprising conducting the cleaning in the same chamber of the single processing apparatus as the vacuum annealing and the forming.

12. The method of claim 1 , wherein forming an insulating material on the silicon material comprises forming the insulating material by atomic layer deposition.

13. The method of claim 5 , wherein vacuum annealing the silicon material comprises moving silicon atoms of the silicon material within the silicon material.

14. A method of forming isolation structures in a single processing apparatus, the method comprising:

vacuum annealing a silicon material comprising mesas and trenches therein, the silicon material being substantially free from contaminants; and

forming an insulating material in the trenches to isolate adjacent mesas of the silicon material from one another,

wherein the vacuum annealing and the forming are conducted in a single processing apparatus.

15. The method of claim 14 , wherein vacuum annealing a silicon material comprises heating the silicon material under vacuum and at a chuck temperature below a melting point of silicon.

16. The method of claim 14 , wherein forming an insulating material in the trenches comprises forming a liner material in the trenches.

17. The method of claim 16 , wherein forming a liner material in the trenches comprises forming the liner material by atomic layer deposition.

18. The method of claim 16 , wherein forming an insulating material in the trenches comprises forming a fill material over the liner material and in the trenches.

19. The method of claim 18 , wherein forming a fill material over the liner material and in the trenches comprises forming shallow trench isolation structures in the trenches.

20. The method of claim 14 , further comprising conducting the vacuum annealing and the forming in different chambers of the single processing apparatus.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2018
From: SANDHU, GURTEJ S.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045838/0903 →