IP Library Granted Patent US 10,215,921
Granted Patent B2
US 10,215,921 · App. 15/648,326 · Granted Feb 26, 2019

Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate

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Quick Facts
Patent No.
US 10,215,921
App. No.
15/648,326
Granted
Feb 26, 2019
Kind
B2
Abstract

Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide is optically decoupled from a support substrate by a shallow trench isolation region.

Claims (11)

1. An integrated structure comprising:

a first semiconductor substrate having a shallow trench isolation region formed therein, the trench of the isolation region being filled with a dielectric material having a first index of refraction, wherein the dielectric material comprises silicon dioxide; and

a second substrate attached to the first substrate and including a dielectric material facing the first substrate and a waveguide formed of a semiconductor material over the dielectric material, the waveguide being formed of a material having a second index of refraction greater than the first index of refraction and being located over the shallow trench isolation region.

2. A structure as in claim 1 , wherein the combined thickness of the dielectric material facing the second substrate and the shallow trench isolation region is at least 1000 nm.

3. A structure as in claim 1 , wherein the first and second substrates comprise silicon.

4. A structure as in claim 1 , wherein the waveguide comprises a core region surrounded by a cladding region, the cladding region being formed at least in part by the dielectric material on the second substrate.

5. A structure as in claim 1 , wherein the core region comprises silicon and the cladding region comprises silicon dioxide.

6. A structure as in claim 1 , further comprising an area of the semiconductor material of the second substrate on which an electronic circuit element is formed.

7. A structure as in claim 1 , wherein the attached first and second substrates form a silicon-on-insulator structure.

8. A structure as in claim 1 , further comprising a dielectric material over the semiconductor material of the second substrate.

9. A structure as in claim 8 , wherein the dielectric material over the semiconductor material of the second substrate is part of an interlayer dielectric structure.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →