Debugging a semiconductor device

1. A method comprising:

receiving with a memory device, implemented at least in part on a die, an instruction to enable a debugging mode of operation; and

in response to receiving the instruction:

modifying functionality of a first non-test pin of the die to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die, modifying the functionality of the first non-test pin comprising changing the first non-test pin from operating as a unidirectional pin to operate as a bidirectional pin;

establishing a debugging clock signal using a signal received at a second non-test pin of the die; and

exchanging information including the debugging data between the die and the debugging component using the first and second non-test pins of the die.

2. The method of claim 1 , wherein receiving the instruction comprises receiving a command including the instruction over a data bus of the die during a normal operating mode of the die.

3. The method of claim 1 , wherein the first non-test pin comprises a reset pin of the die, and wherein the second non-test pin comprises a reference clock pin of the die.

4. The method of claim 1 , wherein the die is placed on a circuit board, wherein the die includes debugging pins that are not coupled to the circuit board, and wherein the information is exchanged with the debugging component using the first and second non-test pins instead of the debugging pins.

5. The method of claim 1 , wherein exchanging the information comprises:

accessing an internal data structure of the memory device to obtain the debugging data; and

transmitting the obtained data over the first non-test pin to the debugging component.

6. The method of claim 5 further comprising:

receiving the information over the first non-test pin from the debugging component; and

modifying contents of the internal data structure based on the received information.

7. The method of claim 1 further comprising determining a point of failure of the memory device based on the exchanged information.

8. The method of claim 1 , wherein the external component comprises a cJTAG interface, wherein the first non-test pin comprises a Universal Flash Storage (UFS) RST_N pin, and the second non-test pint comprises a UFS REF_CLK pin.

9. A method comprising:

receiving with a memory device, implemented at least in part on a die, an instruction to enable a debugging mode of operation; and

in response to receiving the instruction:

modifying functionality of a first non-test pin of the die to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die;

establishing a debugging clock signal using a signal received at a second non-test pin of the die, establishing the debugging clock signal comprising:

receiving, as the debugging clock signal received at the second non-test pin, a reference clock signal with the memory device,

determining a clock frequency associated with a debugging protocol corresponding to the debugging component,

skewing the reference clock signal to match the clock frequency to establish the debugging clock, and

applying the skewed reference clock signal to a debugging device, implemented on the die, associated with the memory device; and

exchanging information including the debugging data between the die and the debugging component using the first and second non-test pins of the die.

10. A system comprising:

control circuitry configured to:

receive with a memory device, implemented at least in part on a die, an instruction to enable a debugging mode of operation; and

in response to receiving the instruction:

modify functionality of a first non-test pin of the die to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die;

establish a debugging clock signal using a signal received at a second non-test pin of the die; and

exchange information including the debugging data between the die and the debugging component using the first and second non-test pins of the die, the first non-test pin comprising a reset pin of the die, and the second non-test pin comprising a reference clock pin of the die.

11. The system of claim 10 , wherein the control circuitry is configured to receive the instruction by receiving a command including the instruction over a data bus of the die during a normal operating mode of the die.

12. The system of claim 10 , wherein the die is placed on a circuit board, wherein the die includes debugging pins that are not coupled to the circuit board, and wherein the information is exchanged with the debugging component using the first and second non-test pins instead of the debugging pins.

13. The system of claim 10 , wherein the control circuitry is configured to modify the functionality of the first non-test pin by changing the first non-test pin from operating as a unidirectional pin to operate as a bidirectional pin.

14. The system of claim 10 , wherein the control circuitry is configured to establish the debugging clock by:

receiving, as the signal received at the second non-test pin, a reference clock signal with the memory device;

determining a clock frequency associated with a debugging protocol corresponding to the debugging component;

skewing the reference clock signal to match the clock frequency to establish the debugging clock; and

applying the skewed reference clock signal to a debugging device, implemented on the die, associated with the memory device.

15. The system of claim 10 , wherein the control circuitry is configured to exchange the information by:

accessing an internal data structure of the memory device to obtain the debugging data; and

transmitting the obtained data over the first non-test pin to the debugging component.

16. The system of claim 15 , wherein the control circuitry is further configured to:

receive the information over the first non-test pin from the debugging component; and

modify contents of the internal data structure based on the received information.

17. The system of claim 10 , wherein the control circuitry is further configured to determine a point of failure of the memory device based on the exchanged information.

18. The system of claim 10 , wherein the external component comprises a cJTAG interface, wherein the first non-test pin comprises a Universal Flash Storage (UFS) RST_N pin, and the second non-test pint comprises a UFS REF_CLK pin.