Power reduction for a sensing operation of a memory cell
View Patent ↗Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor—e.g., that a ferroelectric capacitor may remain polarized at one of two states without a voltage applied across the ferroelectric capacitor—to activate a subset of sensing components corresponding to multiple memory cells with a common word line. For example, a first and second set of memory cells with a common word like may be selected for a read operation. A first set of sensing components corresponding to the first set of memory cells may be activated for the read operation, and a second set of sensing components that correspond to the second set of memory cells may be maintained in a deactivated state.
1. A method, comprising:
selecting a first memory cell coupled with a first digit line and a second memory cell coupled with a second digit line different than the first digit line for an access operation;
activating a first sense component coupled with the first memory cell; and
maintaining a second sense component coupled with the second memory cell in a deactivated state concurrently with activating the first sense component.
2. The method of claim 1 , further comprising:
applying a first voltage to a first switching component coupled with the first memory cell in preparation for the access operation.
3. The method of claim 2 , further comprising:
grounding the first digit line coupled with the first memory cell based at least in part on the applying.
4. The method of claim 2 , further comprising:
applying a second voltage to a second switching component coupled with the second memory cell in preparation for the access operation, wherein the first voltage is different than the second voltage.
5. The method of claim 4 , further comprising:
maintaining the second digit line coupled with the second switching component at the second voltage concurrently with activating the first sense component, wherein the second voltage is based at least in part on a fixed plate line voltage common to the first memory cell and the second memory cell.
6. The method of claim 1 , comprising:
comparing a voltage of the first digit line to a voltage of a reference line based at least in part on the activating, wherein the reference line is coupled to the first sense component; and
determining a logic state of the first memory cell based at least in part on the comparing.
7. The method of claim 6 , further comprising:
activating a word line common to the first memory cell and the second memory cell, wherein activating the first sense component occurs at a fixed elapsed duration after activating the word line.
8. The method of claim 1 , wherein information from the first memory cell is requested and information from the second memory cell is unrequested by the access operation.
9. The method of claim 1 , wherein the first memory cell comprises a first capacitor and the second memory cell comprises a second capacitor.
10. The method of claim 9 , further comprising:
applying a voltage to a word line coupled with the first memory cell; and
establishing a conductive path between the first capacitor of the first memory cell and the first digit line based at least in part on the applying.
11. A memory device, comprising:
a first memory cell coupled with a first sense component;
a second memory cell coupled with a second sense component; and
a controller coupled with the first memory cell and the second memory cell, wherein the controller is operable to activate the first sense component while maintaining the second sense component in a deactivated state.
12. The memory device of claim 11 , further comprising:
a first control line coupled between the first sense component and the controller; and
a second control line coupled between the second sense component and the controller, wherein the first control line is driven by a first driver and the second control line is driven by a second driver.
13. The memory device of claim 12 , wherein the controller is operable to apply a first voltage to the first control line and a second voltage to the second control line, wherein the first voltage is different than the second voltage.
14. The memory device of claim 11 , further comprising:
a plate line common to the first memory cell and the second memory cell.
15. A memory device, comprising:
a first memory cell;
a second memory cell;
a first sense component;
a second sense component; and
a controller coupled with the first sense component and the second sense component, wherein the controller is operable to:
select the first memory cell in electronic communication with a first digit line and the second memory cell in electronic communication with a second digit line different than the first digit line;
activate the first sense component corresponding to the first memory cell; and
maintain the second sense component corresponding to the second memory cell in a deactivated state concurrently with activating the first sense component.
16. The memory device of claim 15 , further comprising:
a first switching component, wherein the controller is operable to apply a first voltage to the first switching component corresponding to the first memory cell.
17. The memory device of claim 15 , further comprising:
a second switching component, wherein the controller is operable to apply a second voltage to the second switching component corresponding to the second memory cell and maintain the second digit line coupled with the second switching component at the second voltage concurrently with activating the first sense component.
18. The memory device of claim 15 , further comprising:
a first control line coupled to the controller; and
a second control line coupled to the controller, wherein the controller is operable to apply a first voltage to the first control line and a second voltage to the second control line, wherein the first voltage is different than the second voltage.
19. The memory device of claim 15 , further comprising:
a reference line corresponding to the first sense component, wherein the controller is operable to compare a voltage of the first digit line to a voltage of the reference line and determine a logic state of the first memory cell based at least in part the voltage of the first digit line.
20. The memory device of claim 15 , further comprising:
a word line corresponding to the first memory cell and the second memory cell, wherein the controller is operable to activate the word line, and wherein activating the first sense component occurs at a fixed time duration after activating the word line.