Non-volatile memory devices and systems with read-only memory features and methods for operating the same
View Patent ↗Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.
1. A memory device, comprising:
a non-volatile memory array; and
circuitry configured to:
store one or more addresses of the non-volatile memory array;
compare an address of a received command to the one or more addresses; and
at least in part based on the comparison, determine not to implement the received command.
2. The memory device of claim 1 , wherein the received command is a write command or an erase command.
3. The memory device of claim 1 , wherein the circuitry is configured to store the one or more addresses in a write-once read-many (WORM) memory of the memory device.
4. The memory device of claim 3 , wherein the circuitry is further configured to:
write the one or more addresses to the write-once read-many (WORM) memory in response to a command received at the memory device.
5. The memory device of claim 3 , wherein the write-once read-many (WORM) memory comprises an array of fuses, anti-fuses, or a combination thereof.
6. The memory device of claim 1 , wherein the circuitry is configured to store the one or more addresses in a mode register of the memory device.
7. The memory device of claim 1 , wherein the circuitry is configured to determine not to implement the received command in response to the received command corresponding to the one or more addresses.
8. The memory device of claim 1 , wherein the circuitry is configured to determine not to implement the received command in response to the received command not corresponding to the one or more addresses.
9. The memory device of claim 1 , wherein the circuitry is further configured to return an error message after determining not to implement the received command.
10. The memory device of claim 1 , wherein the non-volatile memory array comprises NAND flash, NOR flash, MRAM, FeRAM, PCM, or a combination thereof.
11. The memory device of claim 1 , wherein a single semiconductor die comprises the non-volatile memory array and the circuitry.
12. The memory device of claim 1 , wherein a memory controller die comprises the circuitry and a memory die comprises the non-volatile memory array.