Semiconductor devices, and related memory devices and electronic systems
A semiconductor device comprises a stack structure comprising decks each comprising a memory level comprising memory elements, a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to effectuate a portion of control operations for the memory level, and an additional control logic level vertically adjacent and in electrical communication with the memory level and comprising additional control logic devices configured to effectuate an additional portion of the control operations for the memory level. A memory device, a method of operating a semiconductor device, and an electronic system are also described.
1. A semiconductor device, comprising:
a stack structure comprising decks, each of the decks comprising:
a memory level comprising memory elements;
a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to effectuate a portion of control operations for the memory level; and
an additional control logic level vertically adjacent and in electrical communication with the memory level and comprising additional control logic devices configured to effectuate an additional portion of the control operations for the memory level; and
a base control logic structure in electrical communication with the stack structure and comprising further control logic devices configured to effectuate another portion of the control operations for the memory level.
2. The semiconductor device of claim 1 , further comprising:
first interconnect structures extending from and between the base control logic structure and the control logic level of each of the decks of the stack structure; and
second interconnect structures extending from and between the base control logic structure and the additional control logic level of each of the decks of the stack structure.
3. The semiconductor device of claim 2 , wherein:
the first interconnect structures are laterally contained within a first socket area located proximate a first lateral boundary of the stack structure; and
the second interconnect structures are laterally contained within a second, different socket area located proximate a second, different lateral boundary of the stack structure.
4. The semiconductor device of claim 1 , wherein the memory level vertically intervenes between the control logic level and the additional control logic level.
5. The semiconductor device of claim 1 , wherein one or more of the control logic level and the additional control logic level is shared between vertically-neighboring decks of the stack structure.
6. A semiconductor device, comprising:
a stack structure comprising decks, each of the decks comprising:
a memory level comprising an array of memory elements comprising columns of the memory elements and rows of the memory elements;
a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to control column operations for the array of the memory elements; and
an additional control logic level vertically adjacent, overlying, and in electrical communication with the memory level and comprising additional control logic devices configured to control row operations for the array of the memory elements.
7. A semiconductor device, comprising:
a stack structure comprising decks, each of the decks comprising:
a memory level comprising an array of memory elements comprising columns of the memory elements and rows of the memory elements;
a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to control row operations for the array of the memory elements; and
an additional control logic level vertically adjacent, overlying, and in electrical communication with the memory level and comprising additional control logic devices configured to control column operations for the array of the memory elements.
8. The semiconductor device of claim 6 , wherein the control logic level comprises a control device arrangement comprising one or more of a column decoder, sense amplifiers, local I/O devices, and a column repair device.
9. The semiconductor device of claim 6 , wherein the additional control logic level comprises an additional control device arrangement comprising one or more of a row decoder, word line drivers, and a row repair device.
10. The semiconductor device of claim 1 , wherein the control logic level and the additional control logic level each comprise TFT CMOS devices.
11. The semiconductor device of claim 10 , wherein one or more of the TFT CMOS devices comprise:
a first transistor comprising an N-type channel region; and
a second transistor horizontally-neighboring the first transistor and comprising a P-type channel region.
12. The semiconductor device of claim 10 , wherein one or more of the TFT CMOS devices comprise:
a first transistor comprising an N-type channel region; and
a second transistor vertically-neighboring the first transistor and comprising a P-type channel region.
13. A memory device, comprising:
a base control logic structure;
stack structures over the base control logic structure, and each comprising:
a first control logic level over the base control logic structure;
a first memory level over and electrically coupled to the first control logic level;
a first additional control logic level over and electrically coupled to the first memory level;
a second memory level over and electrically coupled to the first additional control logic level; and
a second control logic level over and electrically coupled to the second memory level; and
first interconnect structures extending from the base control logic structure to the first control logic level and the second control logic level of each of the stack structures; and
second interconnect structures extending from the base control logic structure to the first additional control logic level of each of the stack structures.
14. The memory device of claim 13 , wherein the first additional control logic level is configured to partially control operation of each of the first memory level and the second memory level.
15. The memory device of claim 14 , wherein the first additional control logic level is configured to control row operations for arrays of memory elements within the first memory level and the second memory level.
16. The memory device of claim 15 , wherein:
the first control logic level is configured to control column operations for an array of memory elements within the first memory level; and
the second control logic level is configured to control column operations for an additional array of memory elements within the second memory level.
17. The memory device of claim 13 , wherein:
each of the stack structures further comprises:
a third memory level over and electrically coupled to the second control logic level; and
a second additional control logic level over and electrically coupled to the third memory level; and
a portion of the second interconnect structures extend from the base control logic structure to the second additional control logic level of each of the stack structures.
18. The memory device of claim 17 , wherein the second control logic level is configured to partially control operation of each of the second memory level and the third memory level.
19. The memory device of claim 17 , wherein the second control logic level is configured to control column operations for arrays of memory elements within the second memory level and the third memory level.
20. The memory device of claim 13 , wherein the first control logic level, the first additional control logic level, and the second control logic level comprise TFT levels comprising TFT CMOS devices.
21. The memory device of claim 13 , wherein
at least a portion of the first interconnect structures intervene between a first of the stack structures and a second of the stack structures horizontally-neighboring the first of the stack structures in a first direction; and
at least a portion of the second interconnect structures intervene between the first of the stack structures and a third of the stack structures horizontally-neighboring the first of the stack structures in a second direction perpendicular to the first direction.
22. The memory device of claim 13 , wherein one or more of the first interconnect structures and one or more of the second interconnect structures are shared by a first of the stack structures and a second of the stack structures horizontally-neighboring the first of the stack structures.
23. An electronic system, comprising:
at least one input device;
at least one output device;
at least one processor device operably coupled to the input device and the output device; and
at least one memory device operably coupled to the at least one processor device and comprising:
a stack structure comprising decks, each of the decks comprising:
a memory level comprising memory elements;
a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to effectuate a portion of control operations for the memory level; and
an additional control logic level vertically adjacent and in electrical communication with the memory level and comprising additional control logic devices configured to effectuate an additional portion of the control operations for the memory level; and
a base control logic structure in electrical communication with the stack structure and comprising further control logic devices configured to effectuate another portion of the control operations for the memory level.