IP Library Granted Patent US 10,489,085
Granted Patent B2
US 10,489,085 · App. 15/908,261 · Granted Nov 26, 2019

Latency-based scheduling of command processing in data storage devices

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Quick Facts
Patent No.
US 10,489,085
App. No.
15/908,261
Granted
Nov 26, 2019
Kind
B2
Abstract

A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.

Claims (37)

1. A storage device, comprising:

a host interface;

a controller;

non-volatile storage media; and

firmware containing instructions executable by the controller to:

receive, via the host interface, a plurality of commands from a host,

select a subset of commands from the plurality of commands;

schedule the subset for execution during an idle time; and

reduce write amplification in executing the commands in the subset during the idle time;

wherein the non-volatile storage media includes flash memory; and the controller performs garbage collection during the idle time;

wherein the commands of the subset include write commands for storing data in the flash memory;

wherein the write commands in the subset are scheduled in a queue for execution during the idle time in response to the host specifying a quality of service level lower than a threshold for the commands of the subset.

2. The storage device of claim 1 , wherein the write commands are executed after performing garbage collection.

3. The storage device of claim 1 , wherein the write commands are executed in combination with garbage collection.

4. The storage device of claim 1 , wherein the commands of the subset are scheduled in a queue for execution during the idle time in response to the host identifying that the commands of the subset have no requirement in latency performance in completion.

5. The storage device of claim 4 , wherein the write commands are selected for the queue based on an attribute of the write commands.

6. The storage device of claim 5 , wherein the attribute indicates that the write commands stores data non-sequentially in an address space.

7. The storage device of claim 1 , wherein the write commands in the subset are scheduled in a queue for execution during the idle time in response to the host specifying a priority level lower than a threshold for the write commands.

8. The storage device of claim 1 , wherein the controller reduces write amplification via compressing data to be stored via the commands in the subset.

9. The storage device of claim 1 , wherein the controller reduces write amplification via combining write operations in the commands in the subset.

10. The storage device of claim 1 , wherein the controller reduces write amplification via searching a logical to physical address map schedule for execution of the commands in the subset via minimizing write amplification.

11. The storage device of claim 1 , wherein the host interface communicates with the host via a peripheral component interconnect express bus in accordance with a non-volatile memory host controller interface specification.

12. The storage device of claim 11 , wherein the host has a plurality of submission queues to communicate requests to the storage device; and the storage device is determined to be in the idle state at least after the submission queues are empty.

13. A method implemented in a storage device, the method comprising:

receiving, via a host interface of the storage device, a plurality of commands from a host,

selecting, by a controller executing firmware, a subset of commands from the plurality of commands;

scheduling, by the controller, the subset for execution during an idle time; and

reducing, by the controller, write amplification in non-volatile storage media of the storage device in executing the commands in the subset during the idle time;

wherein reducing write amplification includes compressing data of the commands in the subset using a technique different from a compression technique used for commands executed at a non-idle time.

14. The method of claim 13 , wherein reducing write amplification includes searching for a logical to physical address map to minimize write operations.

15. The method of claim 13 , wherein reducing write amplification includes combining write operations of the commands in the subset.

16. A non-transitory computer storage medium storing instructions which, when executed by a storage device, cause the storage device to perform a method, the method comprising:

receiving, via a host interface of the storage device, a plurality of commands from a host,

selecting, by a controller executing firmware, a subset of commands from the plurality of commands;

scheduling, by the controller, the subset for execution during an idle time; and

reducing, by the controller, write amplification in non-volatile storage media of the storage device in executing the commands in the subset during the idle time;

wherein reducing write amplification includes compressing data of the commands in the subset using a technique different from a compression technique used for commands executed at a non-idle time.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2018
From: FROLIKOV, ALEX
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046189/0551 →