IP Library Granted Patent US 10,453,858
Granted Patent B2
US 10,453,858 · App. 15/997,992 · Granted Oct 22, 2019

Methods of forming integrated structures

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Quick Facts
Patent No.
US 10,453,858
App. No.
15/997,992
Granted
Oct 22, 2019
Kind
B2
Abstract

Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.

Claims (20)

1. A method of forming an integrated structure, comprising:

forming a vertical stack of alternating first and second levels; the first levels comprising insulative first material, and the second levels comprising second material;

recessing the first levels relative to the second levels; the second levels having projecting terminal ends extending beyond the recessed first levels; the projecting terminal ends having exposed surfaces of the second material;

forming third material along the exposed surfaces of the second material and around the terminal ends of the second levels; the third material only partially overlapping the first level to leave regions of insulative first material of the first levels exposed;

forming fourth material along the exposed regions of the insulative first material; the third and fourth materials having outer surfaces that form a vertical edge;

forming charge-blocking material extending vertically along the vertical edge;

forming charge-storage material extending vertically along the charge-blocking material;

forming gate-dielectric material extending vertically along the charge-storage material;

forming channel material extending vertically along the gate-dielectric material;

removing the second and third materials to leave voids; and

forming conductive levels within the voids; the conductive levels having primary regions of a first vertical thickness, and having terminal projections of a second vertical thickness which is greater than the first vertical thickness.

2. The method of claim 1 wherein the first levels comprise a third vertical thickness, and wherein the third material is formed to a thickness of less than or equal to about one-third of the third vertical thickness.

3. The method of claim 1 wherein the second and third materials are a same composition as one another.

4. The method of claim 3 wherein the second and third materials comprise silicon nitride.

5. The method of claim 1 wherein the second and third materials are not a same composition as one another.

6. The method of claim 1 wherein the fourth material is electrically insulative.

7. The method of claim 1 wherein each conductive level comprises a conductive core surrounded by an outer conductive layer; with the conductive core comprising a different composition than the outer conductive layer.

8. The method of claim 7 wherein high-k insulative material is formed within the voids and becomes an insulative liner around the outer conductive layer.

9. The method of claim 8 wherein the conductive core is tungsten-containing core, the outer conductive layer comprises metal nitride, and the high-k insulative material comprises aluminum oxide.

10. The method of claim 1 wherein the charge-storage material comprises silicon nitride.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →