IP Library Granted Patent US 10,410,964
Granted Patent B2
US 10,410,964 · App. 16/006,603 · Granted Sep 10, 2019

Methods of forming a semiconductor device comprising first and second nitride layers

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,410,964
App. No.
16/006,603
Granted
Sep 10, 2019
Kind
B2
Abstract

A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.

Claims (61)

1. A semiconductor device comprising:

a first well within semiconductor material;

a second well within the semiconductor material;

a dielectric isolation region within the semiconductor material between the first and second well;

a wiring above and physically contacting the isolation region, the wiring including a seam above the isolation region;

an insulating film over the wiring filling the seam of the wiring; and

another insulating film between the wiring and the insulating film.

2. A semiconductor device comprising:

a first well within semiconductor material;

a second well within the semiconductor material;

a dielectric isolation region within the semiconductor material between the first and second well;

a wiring above and physically contacting the isolation region, the wiring including a seam above the isolation region;

an insulating film over the wiring filling the seam of the wiring; and

an insulative film on the insulating film.

3. A semiconductor device comprising:

a first well within semiconductor material;

a second well within the semiconductor material;

a dielectric isolation region within the semiconductor material between the first and second well;

a wiring above and physically contacting the isolation region, the wiring including a seam above the isolation region;

an insulating film over the wiring filling the seam of the wiring;

a first transistor including a first wiring structure, the first wiring structure including a first gate insulating film between conductive material of the first wiring structure and the first well, a first source and drain disposed on both sides of the first wiring structure within the first well; and

a second transistor including a second wiring structure, the second wiring structure including a second gate insulating film between conductive material of the second wiring structure and the second well, a second source and drain disposed on both sides of the second wiring structure within the second well,

wherein the first wiring structure comprises a first gate electrode of the first transistor,

the second wiring structure comprises a second gate electrode of the second transistor,

the contact plug is electrically connected to at least one of the first source and drain and the second source and drain; and

the isolation region comprises dielectric material.

4. The semiconductor device of claim 3 , wherein the first transistor is an N-channel transistor, and the second transistor is a P-channel transistor.

5. A semiconductor device comprising:

a first well within semiconductor material;

a second well within the semiconductor material;

a dielectric isolation region within the semiconductor material between the first and second well;

a wiring above and physically contacting the isolation region, the wiring including a seam above the isolation region;

an insulating film over the wiring filling the seam of the wiring; and

the wiring comprises a bit line of memory circuitry.

6. A semiconductor device comprising:

a first well within semiconductor material;

a second well within the semiconductor material;

a dielectric isolation region within the semiconductor material between the first and second well;

a wiring including a seam over the isolation region;

an insulating film over the wiring filling the seam of the wiring; and

another insulating film between the wiring and the insulating film, the another insulating film being in the seam; and

the wiring comprises a bit line of memory circuitry.

7. A semiconductor device comprising:

a first well within semiconductor material;

a second well within the semiconductor material;

a dielectric isolation region within the semiconductor material between the first and second well;

a wiring including a seam over the isolation region;

an insulating film over the wiring filling the seam of the wiring; and

another insulating film between the wiring and the insulating film, the another insulating film being in the seam;

an insulative film on the another insulating film; and

the wiring comprises a bit line of memory circuitry.

8. A semiconductor device comprising:

a first well within semiconductor material;

a second well within the semiconductor material;

a dielectric isolation region within the semiconductor material between the first and second well;

a wiring including a seam over the isolation region;

an insulating film over the wiring filling the seam of the wiring; and

another insulating film between the wiring and the insulating film, the another insulating film being in the seam;

an insulative film on the another insulating film;

the insulative film is not in the seam; and

the wiring comprises a bit line of memory circuitry.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →