Memory cells and integrated structures
View Patent ↗A memory cell comprises, in the following order, channel material, a charge-passage structure, charge-storage material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. Dielectric constant (k) of the first material is less than 5.0. Sum of bandgap (BG) and electron affinity (chi) of the second material is no greater than 6.7 eV. The k of the second material is at least 5.0. Sum of BG and chi of the third material is less than 9.0 eV and at least 0.5 eV greater than the sum of the BG and the chi of the second material.
1. A memory cell, comprising, in the following order:
channel material;
a charge-passage structure;
charge-storage material;
a charge-blocking region;
a control gate; and
the charge-passage structure comprising:
a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material;
dielectric constant (k) of the first material being less than 5.0;
sum of bandgap (BG) and electron affinity (chi) of the second material being no greater than 6.7 eV, k of the second material being at least 5.0;
sum of BG and chi of the third material being less than 9.0 eV and at least 0.5 eV greater than the sum of the BG and the chi of the second material;
the first material is directly against the second material and the second material is directly against the third material;
the first material is directly against the channel material and the third material is directly against the charge-storage material; and
at least a majority of the first material is silicon oxide.
2. The memory cell of claim 1 wherein the sum of the BG and the chi of the second material is at least 4.5 eV.
3. The memory cell of claim 2 wherein the sum of the BG and the chi of the second material is at least 5.0 eV.
4. The memory cell of claim 2 wherein the sum of the BG and the chi of the second material is no greater than 6.5 eV.
5. The memory cell of claim 4 wherein the sum of the BG and the chi of the second material is no greater than 6.0 eV.
6. The memory cell of claim 1 wherein the k of the second material is no greater than 60.0.
7. The memory cell of claim 6 wherein the k of the second material is from 10.0 to 40.0.
8. The memory cell of claim 7 wherein the k of the second material is from 10.0 to 25.0.
9. The memory cell of claim 6 wherein the second material comprises at least one of an oxide, a silicate, an aluminate and a gallate of hafnium, zirconium, tantalum, niobium, or titanium, or mixtures of two or more of hafnium, zirconium, tantalum, niobium, and titanium.
10. The memory cell of claim 9 wherein the at least one of oxide, silicate, aluminate and gallate is stoichiometric.
11. The memory cell of claim 9 wherein the at least one of oxide, silicate, aluminate and gallate is non-stoichiometric.
12. The memory cell of claim 9 wherein the at least one of oxide, silicate, aluminate and gallate includes a mixture of two or more of hafnium, zirconium, tantalum, niobium, and titanium.
13. The memory cell of claim 6 wherein the second material is devoid of silicon nitride.
14. The memory cell of claim 1 wherein the sum of the BG and the chi of the third material is at least 5.0 eV.
15. The memory cell of claim 14 wherein the sum of the BG and the chi of the third material is from 7.0 eV to 8.5 eV.
16. The memory cell of claim 15 wherein the sum of the BG and the chi of the third material is from 7.5 eV to 8.0 eV.
17. The memory cell of claim 14 wherein the third material comprises at least one of an oxide, a silicate, an aluminate and a gallate of hafnium, zirconium, tantalum, niobium, or titanium, or mixtures of two or more of hafnium, zirconium, tantalum, niobium, and titanium.
18. A NAND memory array, comprising:
a vertical stack comprising vertically-alternating levels of wordline levels of conductive material and insulating levels of insulator material;
channel material extending elevationally along the vertical stack;
a charge-passage structure laterally outward of and extending elevationally along the channel material, the charge-passage structure comprising:
a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material, the first material is directly against the second material, the second material is directly against the third material, and the first material is silicon oxide;
dielectric constant (k) of the first material being less than 5.0;
sum of bandgap (BG) and electron affinity (chi) of the second material being no greater than 6.7 eV, k of the second material being at least 5.0; and
sum of BG and chi of the third material being less than 9.0 eV and at least 0.5 eV greater than the sum of the BG and the chi of the second material;
charge-storage material laterally outward of the charge-passage structure and within the wordline levels of the conductive material; and
a charge-blocking region within the wordline levels of the conductive material, the charge-blocking region being laterally outward of the charge-passage structure and laterally inward of the conductive material.
19. A NAND memory array, comprising:
a vertical stack comprising vertically-alternating levels of wordline levels of conductive material and insulating levels of insulator material;
channel material extending elevationally along the vertical stack;
a charge-passage structure laterally outward of and extending elevationally along the channel material, the charge-passage structure comprising:
a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material, the first material is directly against the second material, the second material is directly against the third material, and the first material is silicon oxide;
dielectric constant (k) of the first material being from 3.5 to less than 5.0, bandgap (BG) of the first material being from 8.5 eV to 9.5 eV, and electron affinity (chi) of the first material being from 0.7 eV to 1.1 eV;
k of the second material being from 5.0 to 60.0, BG of the second material being from 3.5 eV to 5.0 eV, and chi of the second material being from 1.0 eV to 3.0 eV; and
k of the third material being less than the k of the second material and at least 4.0, BG of the third material being from 4.0 eV to 7.0 eV, and chi of the third material being from 1.0 eV to 2.5 eV;
charge-storage material laterally outward of the charge-passage structure and within the wordline levels of the conductive material; and
a charge-blocking region within the wordline levels of the conductive material, the charge-blocking region being laterally outward of the charge-passage structure and laterally inward of the conductive material.