Modified decode for corner turn
View Patent ↗Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.
1. A method, comprising:
receiving a plurality of data elements each comprising a plurality (M) of units of data to be written to an array of memory cells via a respective M column select components;
performing at least a portion of a corner turn operation on the plurality of data elements by modifying address data units corresponding to positions of the M units of data within the respective data elements on a per column select component basis when writing the plurality of data elements to the array; and
wherein the corner turn operation is an operation that adjusts a storage format of the plurality of data elements.
2. The method of claim 1 , wherein the M column select components each comprise a respective M:1 column select multiplexor.
3. The method of claim 1 , wherein the plurality of data elements comprises M data elements.
4. The method of claim 1 , wherein modifying address data units corresponding to positions of the M units of data within the respective data elements on a per column select component basis further comprises:
providing a plurality of address data units to each of the M column select components; and
modifying the plurality of address data units differently for each of the M column select components.
5. The method of claim 4 , wherein modifying the plurality of address data units differently for each of the M column select components further comprises:
providing the plurality of address data units to a first column select component of the M column select components in an unmodified state; and
providing each of the plurality of address data units to a second column select component of the M column select components in a modified state.
6. The method of claim 5 , wherein modifying the plurality of address data units differently for each of the M column select components further comprises providing the plurality of address data units to at least a third column select component of the M column select components with at least two of the plurality of address data units in a modified state.
7. The method of claim 4 , wherein modifying the plurality of address data units differently for each of the M column select components further comprises performing a binary inversion on address data units being modified.
8. The method of claim 7 , further comprising performing the binary inversion on address data units being modified via exclusive or (XOR) logic gates.
9. The method of claim 8 , further comprising providing a plurality of enable data units to the XOR logic gates, wherein a state of the enable data units determines whether a corresponding address data unit provided to the XOR logic gates is modified.
10. The method of claim 1 , wherein performing the at least the portion of the corner turn operation comprises adjusting the storage format of the plurality of data elements from a first format to a second format.
11. An apparatus, comprising:
a corner turn buffer comprising an array of memory cells, the corner turn buffer used to adjust a storage format of data elements from a first format to a second format; and
decode circuitry coupled to the array and configured to:
receive a plurality data elements each comprising a plurality of (M) units of data to be written to the array via a respective M column select components; and
perform at least a portion of a corner turn operation on the plurality of data elements by modifying address data units corresponding to positions of the M units of data within the respective data elements on a per column select component basis when writing the plurality of data elements to the array.
12. The apparatus of claim 11 , wherein the at least a portion of a corner turn operation is an operation that adjusts a storage format of the plurality of data elements.
13. The apparatus of claim 11 , wherein the array and decode circuitry are located on a controller configured to receive the plurality of data elements from a host.
14. The apparatus of claim 13 , wherein the controller is further configured to:
write the at least one data unit to the array based on the modified address corresponding thereto;
read the at least one data unit out of the array based on the modified address; and
write the at least one data element to a different array of memory cells such that the at least one data element is stored in a consecutive number of memory cells coupled to a same column of the different array.
15. The apparatus of claim 14 , wherein the second array is coupled to sensing components serving as respective 1-bit processors on a per column basis.
16. The apparatus of claim 11 , wherein the decode circuitry comprises logic configured to modify the address data units corresponding to positions of the M units of data within the respective data elements on a per column select component basis when writing the plurality of data elements to the array.
17. The apparatus of claim 16 , wherein the logic configured to modify the address data units comprises:
first logic configured to, for each of the plurality of data elements, modify a first address data unit of the plurality of address data units prior to the plurality of address data units being provided to a first of the plurality of column select components; and
second logic configured to, for each of the plurality of data elements, modify a second address data unit of the plurality of address data units prior to the plurality of address data units being provided to a second of the plurality of column select components.
18. The apparatus of claim 11 , wherein the decode circuitry comprises a plurality of N:1 column select components each corresponding to a different respective N columns of the array and configured to select a particular one of the N columns responsive to states of address data units provided thereto.
19. An apparatus, comprising:
a corner turn buffer comprising a first array of memory cells, the corner turn buffer used to adjust a storage format of data elements from a first format to a second format;
decode circuitry coupled to the array and configured to:
receive a plurality data elements each comprising a plurality of (M) units of data to be written to the array via a respective M column select components; and
perform at least a portion of a corner turn operation on the plurality of data elements by modifying address data units corresponding to positions of the M units of data within the respective data elements on a per column select component basis when writing the plurality of data elements to the first array; and
a second array of memory cells to which the plurality of data elements are written subsequent to being read from the first array in association with performing the corner turn operation.
20. The apparatus of claim 19 , wherein the corner turn operation adjusts a storage format of the plurality of data elements from a horizontal storage format to a vertical storage format.