Real time block failure analysis for a memory sub-system
Several embodiments of memory devices and systems for real time block failure analysis are disclosed herein. In one embodiment, a system includes a memory array including a plurality of memory cells and a processing device coupled to the memory array. The processing device is configured to sense, in response to detection of an error associated with a subset of a plurality of memory cells of the memory device, a state associated with each memory cell of the subset of the plurality of memory cells. The processing device is further configured to store state distribution information in a persistent memory, the state distribution information comprising the sensed state associated with each memory cell of the subset.
1. A system comprising:
a memory array including a plurality of memory cells; and
a processing device coupled to the memory array, the processing device configured to:
in response to detection of an error associated with a subset of the plurality of memory cells, sense a state associated with each memory cell of the subset of the plurality of memory cells; and
store state distribution information in a persistent memory, the state distribution information comprising the sensed state associated with each memory cell of the subset,
wherein sensing the state associated with each memory cell comprises stepping a corresponding word line with a plurality of sensing voltages to determine at which sensing voltage a corresponding bitline output changes, and
wherein storing the state distribution information comprises storing the sensed state associated with each memory cell of the subset in a corresponding disjoint category of a histogram, wherein the corresponding disjoint category of the histogram corresponds to the determined sensing voltage.
2. The system of claim 1 , wherein the sensed state of each memory cell of the subset is a threshold voltage (Vt) stored on each memory cell of the subset.
3. The system of claim 1 , wherein the state associated with each memory cell of the subset is sensed within a predetermined threshold of time from detection of the error.
4. The system of claim 1 , wherein the state associated with each memory cell of the subset is sensed prior to powering off the memory device.
5. The system of claim 1 , wherein the processing device is further configured to sense the state associated with each memory cell of the subset in response to a determination that an error recovery process has failed.
6. The system of claim 1 , wherein the processing device is further configured to:
receive a request for the state distribution information stored in the persistent memory; and
send the state distribution information stored in the persistent memory.
7. The system of claim 1 , wherein the processing device is further configured to store, in the persistent memory, location information indicating a physical location of the subset of the plurality of memory cells within the plurality of memory cells.
8. The system of claim 1 , wherein the subset of the plurality of memory cells is one of a page of memory cells, a block of memory cells, a word line group of memory cells, a plane of memory cells, and a die of memory cells.
9. The system of claim 1 , wherein the processing device is further configured to:
determine, in response to detection of the error, additional information associated with the plurality of memory cells; and
store the additional information in the persistent memory and associate the additional information with the state distribution information.
10. The system of claim 9 , wherein the additional information comprises at least one of:
a die temperature of the memory device,
a power-on time of the memory device,
a number of program operations completed with respect to at least one of the subset of the plurality of memory cells,
a number of erase operations performed with respect to at least one of the subset of the plurality of memory cells,
a combined number of erase and program operations performed with respect to the subset of the plurality of memory cells,
a number of read operations performed with respect to at least one of the subset of the plurality of memory cells,
a read reference voltage associated with the subset of the plurality of memory cells, and
a type of error recovery process attempted prior the state associated with each memory cell of the subset being sensed.
11. The system of claim 1 , wherein the processing device is further configured to sense the state associated with each memory cell of the subset prior to implementation of an error recovery process.
12. A method for storing state information of a memory region of a system, the method comprising:
sensing, in response to detection of an error associated with a subset of a plurality of memory cells of the system, a state associated with each memory cell of the subset of the plurality of memory cells; and
storing state distribution information in a persistent memory, the state distribution information comprising the sensed state associated with each memory cell of the subset,
wherein sensing the state associated with each memory cell comprises stepping a corresponding word line with a plurality of sensing voltages to determine at which sensing voltage a corresponding bitline output changes, and
wherein storing the state distribution information comprises storing the sensed state associated with each memory cell of the subset in a corresponding disjoint category of a histogram, wherein the corresponding disjoint category of the histogram corresponds to the determined sensing voltage.
13. The method of claim 12 , wherein the sensed state of each memory cell of the subset is a threshold voltage (Vt) stored on each memory cell of the subset.
14. The method of claim 12 , wherein the state associated with each memory cell of the subset is sensed within a predetermined threshold of time from detection of the error.
15. The method of claim 12 , further comprising:
receiving a request for the state distribution information stored in the persistent memory; and
sending the state distribution information stored in the persistent memory.
16. A non-transitory computer readable medium having instructions stored thereon that, upon execution by a computing device, cause the computing device to perform operations, wherein the instructions comprise:
instructions to sense, in response to detection of an error associated with a subset of a plurality of memory cells of a system, a state associated with each memory cell of the subset of the plurality of memory cells; and
instructions to store state distribution information in a persistent memory, the state distribution information comprising the sensed state associated with each memory cell of the subset,
wherein the instructions to sense the state associated with each memory cell comprise instructions to step a corresponding word line with a plurality of sensing voltages to determine at which sensing voltage a corresponding bitline output changes, and
wherein the instructions to store the state distribution information comprise instructions to store the sensed state associated with each memory cell of the subset in a corresponding disjoint category of a histogram, wherein the corresponding disjoint category of the histogram corresponds to the determined sensing voltage.
17. The non-transitory computer readable medium of claim 16 , wherein the instructions further comprise instructions to determine that an error recovery process has failed, and wherein the sensing of the state associated with each memory cell of the subset is performed in response to the determination that the error recovery process has failed.
18. The non-transitory computer readable medium of claim 16 , wherein the instructions further comprise instructions to store, in the persistent memory, location information indicating a physical location of the subset of the plurality of memory cells within the plurality of memory cells.