IP Library Granted Patent US 10,809,942
Granted Patent B2
US 10,809,942 · App. 15/927,383 · Granted Oct 20, 2020

Latency-based storage in a hybrid memory system

Inventors: Danilo Caraccio (Milan, IT); Emanuele Confalonieri (Lesmo, IT); Marco Dallabora (Melegnano, IT); Roberto Izzi (Caserta, IT); Paolo Amato (Treviglio, IT); Daniele Balluchi (Cernusco sul Naviglio, IT); Luca Porzio (Casalnuovo di Napoli, IT)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/068G06F3/0611G06F3/0653G06F3/0665G06F12/10G06F2212/1024G06F2212/217
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Quick Facts
Patent No.
US 10,809,942
App. No.
15/927,383
Granted
Oct 20, 2020
Kind
B2
Abstract

An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.

Claims (39)

1. An apparatus, comprising:

a hybrid memory system comprising a first non-volatile memory (NVM) resource, a second NVM resource, and a controller, wherein the controller is configured to:

assign a sensitivity to a command corresponding to performance of a swap operation, the command being associated with a main memory of a host that is separate from and coupleable to the hybrid memory system, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;

determine that the command further corresponds to a particular type of file system write having a determinable write pattern associated therewith;

allocate a portion of the hybrid memory system to store data associated with the main memory of the host that is separate from and coupleable to the hybrid memory system and corresponding to performance of the swap operation, wherein:

the portion of the hybrid memory is allocated to the one of the first NVM or the second NVM that is configured to exhibit a lower access latency and a higher endurance than the other of the first NVM or the second NVM; and

the portion of the hybrid memory is configured to allow data to be transferred between the allocated portion of the hybrid memory system and the host; and

selectively transfer a portion of a page of data of the main memory associated with a virtual memory location of the host to the first NVM or the second NVM of the hybrid memory system as a part of performance of the swap operation by mapping a logical block address (LBA) associated with the main memory of the host to the one of the first NVM or the second NVM that is configured to exhibit the lower access latency and the higher endurance when handling the command based, at least in part, on the assigned sensitivity, the command corresponding to the particular type of file system write, and the particular type of file system write having the determinable write pattern associated therewith, responsive to a determination that a main memory of the host experiences a threshold amount of resource utilization.

2. The apparatus of claim 1 , wherein the controller is further configured to cause the data to be selectively transferred to a particular logical block address range of the hybrid memory system.

3. The apparatus of claim 1 , wherein the controller is further configured to optimize an execution speed of the data by selectively transferring the data in the hybrid memory system.

4. The apparatus of claim 1 , wherein the data includes data corresponding to a process working set of data.

5. The apparatus of claim 1 , wherein at least one of the first NVM and the second NVM comprises a resistance variable memory device and the other of the first NVM and the second NVM comprises a flash memory device.

6. A system, comprising:

a hybrid memory system comprising a first non-volatile memory (NVM) resource, a second NVM resource, and a controller configured to:

assign a sensitivity to a command corresponding to performance of a swap operation, the command being associated with a main memory of a host that is separate from and coupleable to the hybrid memory system, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;

determine that the command further corresponds to a particular type of file system write having a determinable write pattern associated therewith;

allocate a portion of the hybrid memory system to store data associated with the main memory of the host that is separate from and coupleable to the hybrid memory system and corresponding to performance of the swap operation, wherein:

the portion of the hybrid memory is allocated to the one of the first NVM or the second NVM that is configured to exhibit a lower write latency and a higher endurance than the other of the first NVM or the second NVM; and

the portion of the hybrid memory is configured to allow the data to be transferred between the allocated portion of the hybrid memory system and the host;

perform the swap operation by selectively transferring a portion of a page of data of the main memory corresponding to performance of the swap operation from the host to the allocated portion of the hybrid memory system; and

selectively store the portion of a page of data of the main memory in the first NVM or the second NVM of the hybrid memory system as a part of performance of the swap operation by mapping a LBA associated with the main memory of the host coupled to the hybrid memory to the one of the first NVM or the second NVM that is configured to exhibit the lower write latency and the higher endurance when handling the command based, at least in part, on the assigned sensitivity, the command corresponding to the particular type of file system write, and the particular type of file system write having the determinable write pattern associated therewith, wherein the portion of the page of data of the main memory is selectively stored in the first NVM or the second NVM of the hybrid memory based, at least in part on performance of the swap operation.

7. The system of claim 6 , wherein the first memory resource is characterized by at least one of a faster access time and a higher memory endurance than the second memory resource.

8. The system of claim 6 , wherein the controller is configured to optimize an amount of time associated with performance of the swap operation by selectively transferring the data to the allocated portion of the hybrid memory system.

9. The system of claim 6 , wherein the controller is configured to transfer the data back to the host in response to a determination that the data is referenced by the host.

10. The system of claim 6 , wherein the data corresponding to the swap operation corresponds to a process working set of data accessed by a virtual memory page associated with the host.

11. The system of claim 10 , wherein the controller is configured to cause performance of the swap operation in response to a determination that an amount of memory corresponding to the process working set has exceeded a threshold memory consumption value.

12. A method, comprising:

allocating a portion of a hybrid memory system comprising a flash memory device and a resistance variable memory device to store data corresponding to a virtual memory location of a host;

assigning a sensitivity to a command corresponding to performance of a swap operation, the command being associated with a main memory of the host that is separate from and coupleable to the hybrid memory system, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;

determining that the command further corresponds to a particular type of file system write having a determinable write pattern associated therewith;

allocating a portion of the hybrid memory system to store data associated with the main memory of the host that is separate from and coupleable to the hybrid memory system and corresponding to performance of the a swap operation, wherein:

the portion of the hybrid memory is allocated to the one of the flash memory device or the resistance variable memory device that is configured to exhibit a lower access latency and a higher endurance than the other of the flash memory device or the resistance variable memory device; and

the portion of the hybrid memory is configured to allow data to be transferred between the allocated portion of the hybrid memory system and the host; and

selectively transferring a portion of a page of data of the main memory referenced by a virtual memory location associated with the host to the allocated portion of the flash memory device or the resistance variable memory device of the hybrid memory system as a part of performance of the swap operation by mapping a logical block address (LBA) associated with the main memory of the host to the flash memory device or the resistance variable memory device that is configured to exhibit the lower write latency and the higher endurance when handling the command based, at least in part, on the assigned sensitivity, the command corresponding to the particular type of file system write, and the particular type of file system write having the determinable write patter associated therewith.

13. The method of claim 12 , wherein allocating the portion of the hybrid memory system to store the data further comprises allocating the logical block address range of the hybrid memory system to store the data.

14. The method of claim 12 , wherein the data comprises an anonymous page of data.

15. The method of claim 14 , wherein the anonymous page of data includes data corresponding to a process working set of data.

16. The method of claim 12 , further comprising transferring the data from the allocated portion of the hybrid memory system back to the host in response to determining that the host is referencing the data.

17. The method of claim 12 , further comprising selectively transferring the data from the host to the allocated portion of the hybrid memory system in response to determining that a physical memory location associated with the host is referenced by more than one virtual memory location associated with the host.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2018
From: CARACCIO, DANILO; CONFALONIERI, EMANUELE; DALLABORA, MARCO; IZZI, ROBERTO; AMATO, PAOLO; BALLUCHI, DANIELE; PORZIO, LUCA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045302/0017 →
Continuity (1)
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