Hierarchical buffering scheme to normalize non-volatile media raw bit error rate transients

1. A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media, comprising:

writing user data to a set of memory cells in the first media; and

storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells,

wherein the user data includes a second set of parity bits that are distinct from the first set of parity bits and provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.

2. The computer-implemented method of claim 1 , wherein the first set of parity bits includes more bits than the second set of parity bits such that the first set of parity bits provides greater error correction capabilities than the second set of parity bits.

3. The computer-implemented method of claim 1 , further comprising:

storing, in response to writing the user data to the set of memory cells, the user data in a second buffer,

wherein storing the first set of parity bits in the first buffer is performed further in response to an occurrence of a first event.

4. The computer-implemented method of claim 3 , wherein the first event is one of: (a) the second buffer reaching capacity and (b) elapsing of a first period of time since the writing of the user data to the set of memory cells.

5. The computer-implemented method of claim 4 , further comprising:

removing the user data from the second buffer following the occurrence of the first event.

6. The computer-implemented method of claim 5 , further comprising:

removing the first set of parity bits from the first buffer in response to an occurrence of a second event,

wherein the second event is one of: (a) the first buffer reaching capacity and (b) elapsing of a second period of time since the writing of the user data to the set of memory cells, wherein the second period of time extends later in time than the first period of time.

7. The computer-implemented method of claim 6 , further comprising:

receiving a request for the user data;

reading the user data from the second buffer in response to determining that the second event has not occurred;

reading the user data from the set of memory cells and using the first set of parity bits to decode the user data in response to determining that the second event has occurred but the first event has not occurred; and

reading the user data from the set of memory cells and using the second set of parity bits to decode the user data in response to determining that the first event and the second event have occurred.

8. A system comprising:

a memory device comprising a set of memory cells in a first media;

a host interface to receive a request to write user data to the set of memory cells in the first media; and

a processing device operatively coupled to the memory device and the host interface to write the user data to the set of memory cells in the first media and store, in response to receiving the request to write the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells,

wherein the user data includes a second set of parity bits that are distinct from the first set of parity bits and provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.

9. The system of claim 8 , wherein the first set of parity bits includes more bits than the second set of parity bits such that the first set of parity bits provides greater error correction capabilities than the second set of parity bits.

10. The system of claim 8 , wherein the drift management system is to further store, in response to receiving the request to write the user data to the set of memory cells, the user data in a second buffer,

wherein storing the first set of parity bits to the first buffer is performed further in response to an occurrence of a first event.

11. The system of claim 10 , wherein the first event is one of: (a) the second buffer reaching capacity and (b) the elapsing of a first period of time since the writing of the user data to the set of memory cells.

12. The system of claim 11 , wherein the drift management system is to further remove the user data from the second buffer following the occurrence of the first event.

13. The system of claim 12 , wherein the drift management system is to further remove the first set of parity bits from the first buffer in response to an occurrence of a second event,

wherein the second event is one of: (a) the first buffer reaching capacity and (b) the elapsing of a second period of time since the writing of the user data to the set of memory cells, wherein the second period of time is longer than the first period of time.

14. The system of claim 13 , wherein the host interface is to receive a request for the user data, and

wherein the drift management system is to further read the user data from the second buffer in response to determining that the second event has not occurred; read the user data from the set of memory cells and use the first set of parity bits to decode the user data in response to determining that the second event has occurred but the first event has not occurred; and

read the user data from the set of memory cells and use the second set of parity bits to decode the user data in response to determining that the first event and the second event have occurred.

15. A non-transitory machine-readable storage medium, which stores instructions that, when executed by a processor, cause the processor to:

write user data to a set of memory cells in a first media;

store, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells;

receive a request for the user data; and

read the user data from the set of memory cells using the first set of parity bits to decode the user data in response to determining that a first event has not occurred, but a second event has occurred.

16. The non-transitory machine-readable storage medium of claim 15 , wherein the instructions further cause the processor to:

store, in response to writing the user data to the set of memory cells, the user data in a second buffer,

wherein storing the first set of parity bits to the first buffer is performed further in response to an occurrence of the first event, and

wherein the first event is one of the second buffer reaching capacity and the elapsing of a first period of time since the writing of the user data to the set of memory cells.

17. The non-transitory machine-readable storage medium of claim 16 , wherein the instructions further cause the processor to:

remove the user data from the second buffer following the occurrence of the first event.

18. The non-transitory machine-readable storage medium of claim 17 , wherein the instructions further cause the processor to:

remove the first set of parity bits from the first buffer in response to an occurrence of the second event,

wherein the second event is one of: (a) the first buffer reaching capacity and (b) the elapsing of a second period of time since the writing of the user data to the set of memory cells, wherein the second period of time is longer than the first period of time.