Devices, methods, and systems supporting on unit termination
View Patent ↗The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.
1. A system, comprising:
a memory device, wherein:
a memory unit of the memory device includes termination circuitry and a termination matrix, wherein:
the termination circuitry includes different selectable resistors; and
the termination matrix includes resistance values of the different selectable resistors of the termination circuitry, wherein the resistance values represent different input/output speeds at which the memory device operates; and
a memory unit of the memory device does not include termination circuitry.
2. The system of claim 1 , wherein the resistance values represent different clock frequencies at which the memory device operates.
3. The system of claim 1 , wherein the resistance values represent different bus speeds at which the memory device operates.
4. The system of claim 1 , wherein the system includes a controller configured to adjust a timing mode at which the memory device operates.
5. The system of claim 1 , wherein the memory unit of the memory device that includes the termination circuitry and the termination matrix is configured to provide electrostatic discharge protection for the memory unit of the memory device that does not include termination circuitry.
6. The system of claim 1 , wherein the memory unit of the memory device that does not include termination circuitry does not include a termination matrix.
7. A method of operating a system, comprising:
adjusting a timing mode at which a memory device of the system operates, wherein:
a memory unit of the memory device includes termination circuity and a termination matrix, wherein:
the termination circuitry includes different selectable resistors; and
the termination matrix includes resistance values of the different selectable resistors of the termination circuitry, wherein the resistance values represent different clock frequencies at which the memory device operates; and
a memory unit of the memory device does not include termination circuitry.
8. The method of claim 7 , wherein the method includes adjusting the termination circuitry of the memory unit based on the adjustment of the timing mode.
9. The method of claim 8 , wherein adjusting the termination circuitry includes increasing the resistance values of the different selectable resistors of the termination circuitry.
10. The method of claim 8 , wherein adjusting the termination circuitry includes decreasing the resistance values of the different selectable resistors of the termination circuitry.
11. The method of claim 7 , wherein the method includes activating, by the termination circuitry, upon detection of a command to perform a termination function.
12. The method of claim 7 , wherein the method includes de-activating, by the termination circuitry, upon performing a termination function.
13. The method of claim 7 , wherein adjusting the timing mode at which the memory device operates includes adjusting a clock frequency at which the memory device operates.
14. A system, comprising:
a memory device, wherein:
a memory unit of the memory device includes termination circuitry and a termination matrix, wherein:
the termination circuitry includes different selectable resistors; and
the termination matrix includes resistance values of the different selectable resistors of the termination circuitry, wherein the resistance values represent different bus speeds at which the memory device operates; and
a memory unit of the memory device does not include termination circuitry.
15. The system of claim 14 , wherein the termination circuitry is configured to monitor commands provided across a bus of the memory device.
16. The system of claim 15 , wherein the system includes a controller configured to control access across memory channels coupled to the memory device via the bus.
17. The system of claim 14 , wherein the resistance values represent:
different input/output speeds at which the memory device operates; and
different clock frequencies at which the memory device operates.
18. The system of claim 14 , wherein the memory unit of the memory device that includes the termination circuitry and the termination matrix is the only memory unit of the memory device that includes termination circuitry.
19. The system of claim 14 , wherein the memory unit of the memory device that includes the termination circuitry and the termination matrix is configured to perform target termination.
20. The system of claim 14 , wherein the memory unit of the memory device that includes the termination circuitry and the termination matrix is configured to perform non-target termination.