Data strobe multiplexer

1. A system comprising:

a host device including:

a command pin (CMD);

a clock pin (CLK);

a general-purpose input/output (GPIO) pin; and

a data pin, wherein the data pin is one of a set of data pins (DAT[N:0]), wherein N is a positive integer; and

a multiplexer circuit configured to receive a data signal and a data strobe signal from an embedded MultiMediaCard (eMMC) device, and to selectively provide one of the data signal or the data strobe signal to the data pin of the host device,

wherein the host device is configured to receive an output of the multiplexer circuit at the data pin of the host device, to determine a timing relationship between the data strobe signal received from the multiplexer circuit at the data pin of the host device and an internal clock signal in a calibration mode, and to control sampling of the data signal received from the multiplexer circuit at the data pin of the host device using the determined timing relationship in a data read mode,

wherein the host device is configured to:

provide a command to the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device; and

provide a control signal, separate from the command to the eMMC device, to the multiplexer circuit to provide the data strobe signal from the eMMC device at the output of the multiplexer circuit, and

wherein the multiplexer circuit is separate from the eMMC device.

2. The system of claim 1 ,

wherein the multiplexer circuit is configured to receive the data signal from a data pin of the eMMC device and the data strobe signal from a data strobe pin of the eMMC device, and to provide the data signal at the output of the multiplexer circuit in the data read mode and the data strobe signal at the output of the multiplexer circuit in the calibration mode, and

wherein, in the calibration mode, the host device is configured to:

provide the command to the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device;

provide the control signal, separate from the command to the eMMC device, to the multiplexer circuit to provide the data strobe signal from the eMMC device at the output of the multiplexer circuit; and

receive the data strobe signal from the output of the multiplexer circuit at the data pin of the host device.

3. The system of claim 1 , wherein the host device includes:

a delay circuit configured to delay the received output of the multiplexer circuit from the data pin by a configurable delay value; and

a sampling circuit configured to sample the output of the multiplexer circuit at a transition of the internal clock signal,

wherein the host device is configured to adjust the delay value of the delay circuit using the determined timing relationship to align the output of the multiplexer circuit and the internal clock signal for sampling.

4. The system of claim 1 , wherein the host device includes:

a delay circuit configured to delay the received output of the multiplexer circuit from the data pin by a configurable delay value; and

a sampling circuit configured to sample the output of the multiplexer circuit at a transition of the internal clock signal,

wherein the host device is configured to adjust the delay value of the delay circuit, and to sample the output of the multiplexer circuit at different delay values to determine an alignment between the output of the multiplexer circuit and the internal clock signal.

5. The system of claim 1 , including the eMMC device, wherein the data pin of the eMMC device corresponds to the data pin of the host device and the eMMC device includes a dedicated data strobe pin configured to provide the data strobe signal in a high-speed mode, and

wherein the multiplexer circuit includes:

a first input coupled to the data pin of the eMMC device configured to receive read data from the eMMC device;

a second input coupled to the data strobe pin of the eMMC device configured to receive the data strobe signal from the eMMC device;

an output coupled to the data pin of the host device; and

a control input coupled to a general-purpose input/output (GPIO) pin of the host device.

6. The system of claim 1 , wherein, in a calibration mode, the host device is configured to:

provide a control signal to the multiplexer circuit using a general-purpose input/output (GPIO) pin of the host device; and

provide a read command to the eMMC device configured to trigger the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device.

7. The system of claim 5 , wherein, in the data read mode, the host device is configured to:

provide a control signal to the multiplexer circuit using the GPIO pin to couple the data pin of the eMMC device to the output of the multiplexer circuit;

provide a read command to the eMMC device; and

receive read data from the multiplexer circuit at the data pin of the host device.

8. The system of claim 7 , wherein, in the data read mode, the multiplexer circuit is configured to receive the data strobe signal from the eMMC device, but is not configured to provide the data strobe signal to the host device,

wherein the eMMC device includes a dedicated data strobe pin, and

wherein the host device does not include a dedicated data strobe pin.

9. The system of claim 6 , wherein the host device is configured to intermittently trigger the calibration mode to determine the timing relationship between the data strobe signal and the internal clock signal, and to control a delay value of a delay circuit using the determined timing relationship.

10. A method comprising:

providing, using a host device, a command to an eMMC device to provide a data strobe signal on a data strobe pin of the eMMC device;

providing, using the host device, a control signal, separate from the command to the eMMC device, to a multiplexer circuit to provide the data strobe signal from the eMMC device at an output of the multiplexer circuit,

selectively providing, using the multiplexer circuit, one of a data signal or a data strobe signal from an embedded MultiMediaCard (eMMC) device to a data pin of the host device;

receiving an output of the multiplexer circuit at the data pin of the host device;

determining, using the host device, a timing relationship between the data strobe signal received from the multiplexer circuit at the data pin and an internal clock signal in a calibration mode; and

controlling, using the host device, sampling of the received data signal from the multiplexer circuit at the data pin using the determined timing relationship in a data read mode,

wherein the host device includes:

a command pin (CMD);

a clock pin (CLK);

a general-purpose input/output (GPIO) pin; and

a set of data pins (DAT[N:0]), wherein the data pin is one of the set of data pins, and N is a positive integer, and

wherein the multiplexer circuit is separate from the eMMC device.

11. The method of claim 10 , including, in the calibration mode:

providing, using the host device, the command to the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device;

providing the control signal, separate from the command to the eMMC device, to the multiplexer circuit using the host device to provide the data strobe signal from the eMMC device at the output of the multiplexer circuit; and

receiving the data strobe signal from the output of the multiplexer circuit at the data pin of the host device.

12. The method of claim 10 , including:

delaying the received output of the multiplexer circuit from the data pin by a configurable delay value using a delay circuit in the host device;

sampling the output of the multiplexer circuit at a transition of the internal clock signal using a sampling circuit in the host device;

adjusting, using the host device, the delay value of the delay circuit using the determined timing relationship to align the output of the multiplexer circuit and the internal clock signal for sampling.

13. The method of claim 10 , including:

delaying the received output of the multiplexer circuit from the data pin of the host device by a configurable delay value using a delay circuit in the host device;

adjusting, using the host device, the delay value of the delay circuit; and

sampling the output of the multiplexer circuit at a transition of the internal clock signal using a sampling circuit in the host device at different delay values to determine an alignment between the output of the multiplexer circuit and the internal clock signal.

14. The method of claim 10 , including:

providing, using the eMMC device, the data strobe signal at the data strobe pin of the eMMC device in response to a read request in a high-speed mode of the eMMC device;

receiving, using the multiplexer circuit, one of read data from the eMMC device at a first input of the multiplexer circuit or the data strobe signal from the eMMC device in the high-speed mode at a second input of the multiplexer circuit;

controlling, using the host device, an output of the multiplexer circuit using a general-purpose input/output (GPIO) pin of the host device.

15. The method of claim 10 , including, in a calibration mode of the host device:

providing a control signal to the multiplexer circuit using a general-purpose input/output (GPIO) pin of the host device; and

providing a read command to the eMMC device to trigger the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device.

16. The method of claim 15 , including, in the data read mode of the host device:

providing a control signal to the multiplexer circuit using the GPIO pin to couple the data pin of the eMMC device to the output of the multiplexer circuit;

providing a read command to the eMMC device to trigger the eMMC device to provide read data to the data pin; and

receiving read data from the multiplexer circuit at the data pin of the host device.

17. The method of claim 15 , including:

intermittently triggering, using the host device, the calibration mode to determine the timing relationship between the data strobe signal and the internal clock signal, and

controlling, using the host device, a delay value of a delay circuit using the determined timing relationship.

18. A system comprising:

a host device including:

a command pin (CMD);

a clock pin (CLK);

a general-purpose input/output (GPIO) pin; and

a data pin, wherein the data pin is one of a set of data pins (DAT[N:0]), wherein N is a positive integer; and

an embedded MultiMediaCard (eMMC) device including a data pin and a dedicated data strobe pin configured to provide a data strobe signal in a high-speed mode;

a multiplexer circuit separate from the eMMC device, the multiplexer circuit including a first input coupled to a data pin of the eMMC device configured to receive read data from the eMMC device, a second input coupled to a data strobe pin of the eMMC device configured to receive the data strobe signal from the eMMC device, a control input coupled to the GPIO pin of the host device, and an output coupled to the data pin of the host device configured to selectively provide one of the data signal or the data strobe signal from the eMMC device to the host device,

wherein, in a calibration mode, the host device is configured to:

provide a control signal to the multiplexer circuit using the GPIO pin to couple the data strobe pin of the eMMC device to the output of the multiplexer circuit;

provide a read command to the eMMC device separate from the control signal to the multiplexer circuit, the read command configured to trigger the eMMC device to provide the data strobe signal on the data strobe pin;

receive the data strobe signal from the output of the multiplexer circuit at the data pin of the host device; and

determine a timing relationship between an internal clock signal and the data strobe signal received at the data pin of the host device from the multiplexer circuit, and wherein the data pin of the eMMC device corresponds to the data pin of the host device.

19. The system of claim 18 , wherein, in a data read mode, the host device is configured to:

provide a control signal to the multiplexer circuit using the GPIO pin to couple the data pin of the eMMC device to the output of the multiplexer circuit;

provide a read command to the eMMC device;

receive read data from the multiplexer circuit at the data pin of the host device; and

control sampling of the received read data from the multiplexer circuit at the data pin using the determined timing relationship.