Assemblies having conductive structures along pillars of semiconductor material
Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.
1. An assembly, comprising:
pillars of semiconductor material over a base, the pillars of semiconductor material being arranged in rows that extend along a first direction;
the rows further comprising an intervening spacing regions between the pillars of semiconductor material such that the intervening spacing regions alternate with the silicon pillars within each of the rows,
the pillars of semiconductor material having top surfaces at a first maximum height above the base, and the intervening spacing regions comprising spacing structures having top surfaces at a second maximum height above the base, the second maximum height being below the first maximum height;
the rows being spaced from each other by gap regions;
conductive structures within the gap regions between the rows, the conductive structures each extending along the first direction along a plurality of the pillars of semiconductive material, two of the conductive structures being within each of the gap regions and being spaced apart from one another by a separating region, the separating region having a bottom surface that undulates across semiconductor segments and insulative segments, a height of each of the semiconductor segments being higher than that of each of the insulative segments relative to the base;
channel regions within the pillars of semiconductor material;
gates within the conductive structures; and
transistors, with each of the transistors comprising one of the channel regions and at least one of the gates.
2. The assembly of claim 1 , wherein the semiconductor segments and the insulative segments alternate with one another along the first direction.
3. The assembly of claim 1 , wherein the spacing structures are insulative.
4. The assembly of claim 1 , wherein the spacing structures are conductive.
5. The assembly of claim 1 , wherein the conductive structures are comprised by wordlines; and the assembly further comprising:
digit lines under the pillars of semiconductor material and extending along a second direction which intersects the first direction;
memory cells coupled with the transistors, with each of the memory cells being uniquely addressed by one of the wordlines in combination with one of the digit lines.