Error correction using hierarchical decoders
View Patent ↗Apparatuses and methods related to correcting errors can include using fast decoding (FD) decoders and accurate decoding (AD) decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.
1. A memory device, comprising:
an array;
a first decoder coupled to the array and configured to:
receive input data from the memory array;
perform a plurality of operations associated with an error detection on the input data; and
provide, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device wherein the validation flag triggers or inhibits the second decoder.
2. The memory device of claim 1 , wherein the first decoder is further configured to determine that the input data does not contain an error.
3. The memory device of claim 2 , wherein the first decoder is further configured to provide the input data as the output data based on determining that the input data does not contain the error.
4. The memory device of claim 1 , wherein the first decoder is further configured to determine that the input data contains an error.
5. The memory device of claim 4 , wherein the first decoder is further configured to correct the error to generate the output data.
6. The memory device of claim 4 , wherein the first decoder is further configured to pass the input data as the output data based on a determination not to correct the error.
7. The memory device of claim 4 , wherein the validity flag describes whether the error is corrected in the output data.
8. The memory device of claim 1 , wherein the plurality of parity bits is used to conduct the error detection.
9. The memory device of claim 1 , wherein the first decoder and the second decoder are error-correcting code decoders.
10. The memory device of claim 1 , wherein the decoder is a fast decoding (FD) decoder.
11. The memory device of claim 1 , wherein the second decoder is an error-correcting code decoder.
12. The memory device of claim 1 , wherein the second decoder is an accurate decoding (AD) decoder.
13. A controller coupled to a memory device, comprising:
an accurate decoding (AD) decoder hosted by the controller and configured to:
receive data, a validity flag, and parity bits from a first fast decoding (FD) decoder hosted by the memory device;
responsive to determining that the validity flag is a first value, provide the data and the parity bits to a second FD decoder;
responsive to determining that the validity flag is a second value:
perform error correction operations on the data using the parity bits;
provide the data as corrected and the parity bits to the second FD decoder; and
the second FD decoder hosted by the controller and configured to perform error correction on the data using the parity bits.
14. The controller of claim 13 , wherein the AD decoder is further configured to receive corrected data if the validity flag comprises the first value.
15. The controller of claim 13 , wherein the AD decoder is further configured to receive raw data if the validity flag comprises the second value.
16. The controller of claim 13 , wherein the controller is a micro controller.
17. The controller of claim 13 , wherein the AD decoder is an inner decoder and the second FD decoder is an outer decoder.
18. An apparatus, comprising:
a memory array, configured to store data and parity bits; and
a fast decoding (FD) decoder coupled to the memory array and configured to receive the data and the parity bits and comprising:
a syndrome computation unit configured to generate a syndrome from the data and the parity bits;
an error correction unit configured to:
perform an error correction code on the data using the syndrome and the parity bits to generate corrected data based on a determination to correct the data; and
provide at least one of the data and the corrected data to an accurate decoding (AD) decoder hosted by a controller; and
a miscorrection checker unit configured to:
generate a validity flag based on whether the error correction unit provides the data or the corrected data to the AD decoder; and
provide the validity flag to the AD decoder wherein the validation flag triggers or inhibits the AD decoder.
19. The apparatus of claim 18 , wherein the miscorrection checker unit is further configured to generate the validity flag based on the syndrome provided by the syndrome computation unit.
20. The apparatus of claim 18 , wherein the miscorrection checker unit is further configured to receive a message, from the error correction unit, describing whether the error correction unit provided the at least one of the data or the corrected data to the AD decoder.
21. The apparatus of claim 18 , wherein FD decoder further comprises a parity bits line.
22. The apparatus of claim 21 , wherein the FD decoder is further configured to provide the parity bits to the AD decoder based on a determination to provide the data to the AD decoder.
23. The apparatus of claim 22 , wherein the FD decoder is further configured to provide the parity bits to the AD decoder based on a request to provide the parity bits.
24. A method for performing an error correction code using a fast decoding (FD) decoder, comprising:
determining whether to perform, using the FD decoder hosted by a memory device, a first error correction code on a page;
based on a determination to perform the first error correction:
generating a corrected page from the page and parity bits; and
generating a first validity flag;
providing the first validity flag and the corrected page to an accurate decoding (AD) decoder hosted by a micro controller wherein the first validation flag inhibits the AD decoder; and
based on a determination not to perform the first error correction code;
generating a second validity flag;
providing the second validity flag, the page, and the parity bits to the AD decoder hosted by the micro controller wherein the second validation flag triggers the AD decoder.
25. The method of claim 24 , further comprising, based on receiving the second validity flag, performing a second error correction code on the page using the parity bits using the AD decoder hosted by the micro controller.
26. The method of claim 25 , wherein the AD decoder utilizes sequential logic.
27. The method of claim 24 , further comprising based on receiving the first validity flag, abstaining from performing a second error correction code on the page.
28. The method of claim 24 , wherein the FD decoder utilizes algebraic decoding.
29. The method of claim 28 , wherein the FD decoder utilizes combinatory logic.