Tapered memory cell profiles
Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.
1. A memory device, comprising:
a self-selecting memory component comprising a bottom surface having a first bottom length and a top surface having a first top length less than the first bottom length in a first direction, the bottom surface having a second bottom length and the top surface having a second top length equal to the second bottom length in a second direction;
a top electrode coupled with the top surface of the self-selecting memory component; and
a bottom electrode coupled with the bottom surface of the self-selecting memory component and in electronic communication with the top electrode via the self-selecting memory component.
2. The memory device of claim 1 , wherein a cross-section of the self-selecting memory component comprises a rectangle in the second direction.
3. The memory device of claim 1 , wherein a cross-section of the self-selecting memory component comprises a trapezoid in the first direction.
4. The memory device of claim 1 , wherein the bottom surface has a greater area than the top surface.
5. The memory device of claim 1 , wherein the self-selecting memory component comprises a chalcogenide material.
6. The memory device of claim 1 , further comprising:
a word line in electronic communication with the bottom electrode in the first direction, wherein the bottom surface having a greater area than the top surface is coupled with the word line; and
a digit line in electronic communication with the top electrode in the first direction.
7. The memory device of claim 1 , wherein a taper from the bottom surface to the top surface comprises a stepped taper.
8. The memory device of claim 7 , wherein the taper is configured to mitigate shorts in adjacent word lines.
9. The memory device of claim 1 , further comprising:
a second self-selecting memory component that tapers from a second bottom surface to a second top surface opposite the second bottom surface,
wherein the bottom surface of the self-selecting memory component includes a first edge and the second bottom surface of the second self-selecting memory component includes a second edge, the top surface of the self-selecting memory component includes a third edge and the second top surface of the second self-selecting memory component includes a fourth edge, wherein a distance between the first edge and the second edge is less than a distance between the third edge and the fourth edge.
10. A memory device, comprising:
a self-selecting memory component comprising a top surface having a first top length and a bottom surface having a first bottom length less than the first top length in a first direction, the top surface having a second top length and the bottom surface having a second bottom length in a second direction, the second direction different than the first direction, wherein the second top length of the top surface is greater than the second top length of the bottom surface in the second direction;
a top electrode coupled with the top surface of the self-selecting memory component; and
a bottom electrode coupled with the bottom surface of the self-selecting memory component and in electronic communication with the top electrode via the self-selecting memory component.
11. The memory device of claim 10 , wherein the second top length of the top surface is equal to the second bottom length of the bottom surface in the second direction.
12. The memory device of claim 10 , wherein a cross-section of the self-selecting memory component comprises an inverted trapezoid in the second direction.
13. The memory device of claim 10 , wherein the bottom surface has a smaller area than the top surface.
14. The memory device of claim 10 , wherein a cross-section of the self-selecting memory component comprises an inverted trapezoid in the first direction.
15. The memory device of claim 10 , wherein the self-selecting memory component comprises a frustum.
16. The memory device of claim 10 , wherein a taper from the top surface to the bottom surface is configured to increase a distance between adjacent word lines.
17. A method, comprising:
performing a read operation on a self-selecting memory component that tapers from a first surface to a second surface opposite the first surface, the second surface having an area smaller than an area of the first surface;
applying a voltage having a positive polarity to the first surface of the self-selecting memory component based at least in part on performing the read operation; and
outputting a logic state stored on the self-selecting memory component based at least in part on applying the positive polarity to the first surface of the self-selecting memory component that is greater than the second surface.
18. The method of claim 17 , wherein the first surface is a bottom surface coupled with a word line and the second surface is a top surface coupled with a digit line.
19. The method of claim 17 , wherein the first surface is a top surface coupled with a digit line and the second surface is a bottom surface coupled with a word line.
20. The method of claim 17 , wherein the first surface is a coupled with a word line extending in a first direction and the second surface being coupled with a plurality of digit lines extending in a second direction different from the first direction.